AT91SAM7S161-AU Atmel, AT91SAM7S161-AU Datasheet - Page 394
![IC MCU ARM7 16KB FLASH 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT91SAM7S161-AU
Manufacturer Part Number
AT91SAM7S161-AU
Description
IC MCU ARM7 16KB FLASH 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S161-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7S161-AU
Manufacturer:
NXP
Quantity:
3
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31.7.6
Name:
Access Type:
Note:
• RXRDY: Receiver Ready
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were
being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been
requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• RXBRK: Break Received/End of Break
0: No Break received or End of Break detected since the last RSTSTA.
1: Break Received or End of Break detected since the last RSTSTA.
• ENDRX: End of Receiver Transfer
0: The End of Transfer signal from the Receive PDC channel is inactive.
1: The End of Transfer signal from the Receive PDC channel is active.
• ENDTX: End of Transmitter Transfer
0: The End of Transfer signal from the Transmit PDC channel is inactive.
1: The End of Transfer signal from the Transmit PDC channel is active.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has been detected low since the last RSTSTA.
394
PARE
CTS
31
23
15
–
–
7
1. DCDIC, DSRIC and RIIC do not pertain to the AT91SAM7S32/16.
AT91SAM7S Series Preliminary
USART Channel Status Register
FRAME
DCD
30
22
14
US_CSR
Read-only
–
–
6
NACK
OVRE
DSR
29
21
13
–
5
RXBUFF
ENDTX
28
20
12
RI
–
4
TXBUFE
ENDRX
CTSIC
27
19
11
–
3
ITERATION
DCDIC
RXBRK
26
18
10
–
2
(1)
TXEMPTY
DSRIC
TXRDY
25
17
–
9
1
(1)
6175K–ATARM–30-Aug-10
TIMEOUT
RXRDY
RIIC
24
16
–
8
0
(1)
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