ATMEGA8-16AU Atmel, ATMEGA8-16AU Datasheet - Page 19
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ATMEGA8-16AU
Manufacturer Part Number
ATMEGA8-16AU
Description
IC AVR MCU 8K 16MHZ 5V 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Data Memory
Access Times
EEPROM Data
Memory
EEPROM Read/Write
Access
2486Z–AVR–02/11
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 9. On-chip Data SRAM Access Cycles
The ATmega8 contains 512bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
below, specifying the EEPROM Address Registers, the EEPROM Data Register, and the
EEPROM Control Register.
“Memory Programming” on page 215
in SPI- or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used.
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
See “Preventing EEPROM Corruption” on page 23.
“The EEPROM Control Register – EECR” on page 20
Address
clk
CC
Data
Data
WR
CPU
RD
is likely to rise or fall slowly on Power-up/down. This causes the device for
Compute Address
T1
Memory Vccess Instruction
contains a detailed description on EEPROM Programming
Address Valid
CPU
T2
Table 1 on page
cycles as described in
for details on how to avoid problems in
for details on this.
Next Instruction
T3
21. A self-timing function,
ATmega8(L)
Figure
9.
19
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