ATMEGA8-16AU Atmel, ATMEGA8-16AU Datasheet - Page 98
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ATMEGA8-16AU
Manufacturer Part Number
ATMEGA8-16AU
Description
IC AVR MCU 8K 16MHZ 5V 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 39. Waveform Generation Mode Bit Description (Continued)
Note:
Timer/Counter 1
Control Register B –
TCCR1B
98
Mode
10
11
12
13
14
15
7
8
9
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the
WGM13
ATmega8(L)
location of these bits are compatible with previous versions of the timer
0
1
1
1
1
1
1
1
1
WGM12
(CTC1)
1
0
0
0
0
1
1
1
1
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the
Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see
41 on page 94
Bit
Read/Write
Initial Value
(PWM11)
WGM11
1
0
0
1
1
0
0
1
1
ICNC1
(PWM10)
R/W
and
WGM10
7
0
1
0
1
0
1
0
1
0
1
Figure 42 on page
ICES1
R/W
6
0
Timer/Counter Mode of
Operation
Fast PWM, 10-bit
PWM, Phase and Frequency Correct
PWM, Phase and Frequency Correct
PWM, Phase Correct
PWM, Phase Correct
CTC
(Reserved)
Fast PWM
Fast PWM
R
5
–
0
(1)
WGM13
94.
R/W
0
4
WGM12
WGM
R/W
3
0
12:0 definitions. However, the functionality and
CS12
R/W
2
0
TOP
0x03FF
ICR1
OCR1A
ICR1
OCR1A
ICR1
–
ICR1
OCR1A
CS11
R/W
1
0
Update of
OCR1
BOTTOM
BOTTOM
BOTTOM
TOP
TOP
Immediate
–
BOTTOM
BOTTOM
CS10
R/W
0
0
x
TCCR1B
2486Z–AVR–02/11
TOV1 Flag
Set on
TOP
BOTTOM
BOTTOM
MAX
–
TOP
BOTTOM
BOTTOM
TOP
Figure