PIC16LC72A-04I/ML Microchip Technology, PIC16LC72A-04I/ML Datasheet - Page 14
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PIC16LC72A-04I/ML
Manufacturer Part Number
PIC16LC72A-04I/ML
Description
IC MCU OTP 2KX14 A/D PWM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC72A-04I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, SPI, SSP
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
22
Number Of Timers
8
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC16LC72A04I/ML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LC72A-04I/ML
Manufacturer:
Microchip Technology
Quantity:
135
PIC16C62B/72A
2.2.2.4
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4:
DS35008B-page 14
bit7
bit 7:
bit 6:
bit 5-4: Unimplemented: Read as ‘0’
bit 3:
bit 2:
bit 1:
bit 0:
Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this
U-0
—
PIE1 REGISTER
Unimplemented: Read as ‘0’
ADIE
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
bit clear.
ADIE
R/W-0
(1)
(1)
: A/D Converter Interrupt Enable bit
PIE1 REGISTER (ADDRESS 8Ch)
U-0
—
U-0
—
SSPIE
R/W-0
Preliminary
CCP1IE
R/W-0
TMR2IE
R/W-0
Note:
TMR1IE
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
1999 Microchip Technology Inc.
read as ‘0’