AT89LP6440-20PU Atmel, AT89LP6440-20PU Datasheet - Page 4
![MCU 8051 64K FLASH ISP 40PDIP](/photos/6/70/67049/453-40-dip_sml.jpg)
AT89LP6440-20PU
Manufacturer Part Number
AT89LP6440-20PU
Description
MCU 8051 64K FLASH ISP 40PDIP
Manufacturer
Atmel
Series
89LPr
Datasheet
1.AT89LP6440-20MU.pdf
(194 pages)
Specifications of AT89LP6440-20PU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1.5
Table 1-1.
4
TQFP
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Pin Description
PLCC
AT89LP6440 - Preliminary
Pin Number
10
11
12
13
14
15
16
17
18
19
20
21
22
7
8
9
AT89LP6440 Pin Description
PDIP
N/A
10
11
12
13
14
15
16
17
18
19
6
7
8
9
VQFN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Symbol
GND
P1.5
P1.6
P1.7
P4.2
P3.0
VDD
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.1
P4.0
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
Description
P1.5: User-configurable I/O Port 1 bit 5.
MOSI: SPI master-out/slave-in. When configured as master, this pin is an output.
When configured as slave, this pin is an input.
GPI5: General-purpose Interrupt input 5.
P1.6: User-configurable I/O Port 1 bit 6.
MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When
configured as slave, this pin is an output.
GPI6: General-purpose Interrupt input 6.
P1.7: User-configurable I/O Port 1 bit 7.
SCK: SPI Clock. When configured as master, this pin is an output. When configured
as slave, this pin is an input.
GPI7: General-purpose Interrupt input 7.
P4.2: User-configurable I/O Port 4 bit 2 (if Reset Fuse is disabled).
RST: External Active-Low Reset input (if Reset Fuse is enabled.
Reset” on page
DCL: Serial Clock input for On-Chip Debug Interface when OCD is enabled.
P3.0: User-configurable I/O Port 3 bit 0.
RXD: Serial Port Receiver Input.
Supply Voltage
P3.1: User-configurable I/O Port 3 bit 1.
TXD: Serial Port Transmitter Output.
P3.2: User-configurable I/O Port 3 bit 2.
INT0: External Interrupt 0 Input or Timer 0 Gate Input.
P3.3: User-configurable I/O Port 3 bit 3.
INT1: External Interrupt 1 Input or Timer 1 Gate Input
P3.4: User-configurable I/O Port 3 bit 4.
T1: Timer/Counter 0 External input or PWM output.
P3.5: User-configurable I/O Port 3 bit 5.
T1: Timer/Counter 1 External input or PWM output.
P3.6: User-configurable I/O Port 3 bit 6.
WR: External memory interface Write Strobe (active-low).
P3.7: User-configurable I/O Port 3 bit 7.
RD: External memory interface Read Strobe (active-low).
P4.1: User-configurable I/O Port 4 bit 1.
XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the
internal RC oscillator is selected as the clock source.
CLKOUT: When the internal RC oscillator is selected as the clock source, may be
used to output the internal clock divided by 2.
DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and
the external clock is selected as the clock source.
P4.0: User-configurable I/O Port 4 bit 0.
XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits.
It may be used as a port pin if the internal RC oscillator is selected as the clock
source.
DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and
the internal RC oscillator is selected as the clock source.
Ground
34.).
See “External
3706A–MICRO–9/09
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