AT89LP6440-20PU Atmel, AT89LP6440-20PU Datasheet - Page 74

• Manufacturer Part Number: AT89LP6440-20PU
• Description: MCU 8051 64K FLASH ISP 40PDIP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.3
13.3.1
74
Output Compare Mode
AT89LP6440 - Preliminary
Waveform Generation
The Compare/Capture Array provides a variety of compare modes suitable for event timing or
waveform generation. CCA channels are configured for compare mode by setting the CCMx bit
in the associated CCCx register to 1. A compare event occurs when the 16-bit contents of a
channel’s data register match the contents of Timer 2 (TH2 and TL2). The compare event also
sets the channel’s interrupt flag CCFx in T2CCF and may optionally clear Timer 2 to 0000H if the
CTCx bit in CCCx is set. A diagram of a CCA channel in compare mode is shown in
Figure 13-3. CCA Compare Mode Diagram
Each CCA channel has an associated external compare output pin: CCA (P2.0), CCB (P2.1),
CCC (P2.2) and CCD (P2.3). The CxM
compare event occurs. The output pin may be set to 1, cleared to 0 or toggled. Output actions
take place even if the interrupt is disabled; however, the associated I/O pin must be set to the
desired output mode before the compare event occurs. The state of the compare outputs are ini-
tialized to 1 by reset. Channels C and D cannot use their output pin when the DAC is enabled.
These channels may still be used to generate interrupts or to clear the timebase. The same
applies to all four channels when Port 2 is used for the external memory interface.
Multiple compare events per channel can occur within a single time period, provided that the
software has time to update the compare value before the timer reaches the next compare point.
In this case other interrupts should be disabled or the CCA interrupt given a higher priority in
order to ensure that the interrupt is serviced in time.
A wide range of waveform generation configurations are possible using the various operating
modes of Timer 2 and the CCA. Some example configurations are detailed below. Pulse width
modulation is a special case of output compare. See
PWM operation.
T2CCL
CCxL
00H
TL2
shadow
T2CCH
CCxH
00H
TH2
=
T2CCC
CCCx
2-0
CTCx
bits in CCCx determine what action is taken when a
Section 13.4 on page 76
CCFx
CxM
2-0
CIENx
Interrupt
for more details of
CCx (P2.x)
3706A–MICRO–9/09
Figure
13-3.