ATMEGA8515-16PU Atmel, ATMEGA8515-16PU Datasheet - Page 135
![IC AVR MCU 8K 16MHZ 5V 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA8515-16PU
Manufacturer Part Number
ATMEGA8515-16PU
Description
IC AVR MCU 8K 16MHZ 5V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8515-16PU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Cpu Speed
16 MIPS
Eeprom Memory
512 Bytes
Input Output
35
Interface
SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
8K Bytes
Timers
1-8-bit, 1-16-bit
Voltage, Range
4.5-5.5 V
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
35
Number Of Timers
2
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8515-16PU
Manufacturer:
AT
Quantity:
20 000
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- Download datasheet (2Mb)
USART
Single USART
2512K–AVR–01/10
The Universal Synchronous and Asynchronous serial Receiver and Transmitter
(USART) is a highly flexible serial communication device. The main features are:
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The ATmega8515 has one USART. The functionality for the USART is described below.
Note that in AT90S4414/8515 compatibility mode, the double buffering of the USART
Receive Register is disabled. For details, see “AVR USART vs. AVR UART – Compati-
bility” on page 137.
A simplified block diagram of the USART Transmitter is shown in Figure 64. CPU acces-
sible I/O Registers and I/O pins are shown in bold.
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
ATmega8515(L)
135
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