ATMEGA8515-16PU Atmel, ATMEGA8515-16PU Datasheet - Page 27

• Manufacturer Part Number: ATMEGA8515-16PU
• Description: IC AVR MCU 8K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Cpu Speed: 16 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 35
• Interface: SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 8K Bytes
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 4.5-5.5 V
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Pull-up and Bus Keeper
Timing
2512K–AVR–01/10
The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port
Register is written to one. To reduce power consumption in sleep mode, it is recom-
mended to disable the pull-ups by writing the Port Register to zero before entering
sleep.
The XMEM interface also provides a bus keeper on the AD7:0 lines. The bus keeper
can be disabled and enabled in software as described in “Special Function IO Register –
SFIOR” on page 31. When enabled, the bus keeper will keep the previous value on the
AD7:0 bus while these lines are tri-stated by the XMEM interface.
External memory devices have various timing requirements. To meet these require-
ments, the ATmega8515 XMEM interface provides four different wait states as shown in
Table 3. It is important to consider the timing specification of the external memory
device before selecting the wait state. The most important parameters are the access
time for the external memory in conjunction with the set-up requirement of the
ATmega8515. The access time for the external memory is defined to be the time from
receiving the chip select/address until the data of this address actually is driven on the
bus. The access time cannot exceed the time from the ALE pulse is asserted low until
data must be stable during a read sequence (t
105 on page 204). The different wait states are set up in software. As an additional fea-
ture, it is possible to divide the external memory space in two sectors with individual wait
state settings. This makes it possible to connect two different memory devices with dif-
ferent timing requirements to the same XMEM interface. For XMEM interface timing
details, please refer to Figure 89 to Figure 92, and Table 98 to Table 105.
Note that the XMEM interface is asynchronous and that the waveforms in the figures
below are related to the internal system clock. The skew between the Internal and Exter-
nal clock (XTAL1) is not guaranteed (it varies between devices, temperature, and supply
voltage). Consequently, the XMEM interface is not suited for synchronous operation.
Figure 13. External Data Memory Cycles without Wait State (SRWn1 = 0 and
SRWn0 = 0)
Note:
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector)
The ALE pulse in period T4 is only present if the next instruction accesses the RAM
(internal or external).
(1)
DA7:0
A15:8
CPU
ALE
WR
RD
)
Prev. Addr.
Prev. Data
Prev. Data
Prev. Data
T1
Address
Address
Address
T2
XX
LLRL
+ t
RLRH
Address
T3
ATmega8515(L)
Data
Data
Data
- t
DVRH
in Table 98 to Table
T4
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