PIC18LF2221-I/SP Microchip Technology, PIC18LF2221-I/SP Datasheet - Page 176
![IC PIC MCU FLASH 2KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2221-I/SP
Manufacturer Part Number
PIC18LF2221-I/SP
Description
IC PIC MCU FLASH 2KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18LF2221-IML.pdf
(394 pages)
6.PIC18F2321-IML.pdf
(396 pages)
Specifications of PIC18LF2221-I/SP
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18LF2221-IML PDF datasheet #5
- PIC18F2321-IML PDF datasheet #6
- Current page: 176 of 394
- Download datasheet (7Mb)
PIC18F4321 FAMILY
REGISTER 17-5:
REGISTER 17-6:
DS39689A-page 174
bit 0
bit 7-0
SSPCON2: MSSP CONTROL REGISTER 2 (I
SSPADD: MSSP ADDRESS REGISTER
bit 7
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Legend:
R = Readable bit
-n = Value at POR
bit 7
ADD<7:0>: MSSP Address bits
Legend:
R = Readable bit
-n = Value at POR
GCEN
R/W-0
R/W-0
ADD7
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
Note 1: MSSP Address register in 1
may not be set (no spooling) and the SSPBUF may not be written (or writes to the
SSPBUF are disabled).
mode.
ACKSTAT
R/W-0
R/W-0
ADD6
Advance Information
ADMSK5
ACKDT/
R/W-0
R/W-0
ADD5
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
ACKEN
ADMSK4
2
R/W-0
R/W-0
ADD4
C Slave mode. MSSP Baud Rate register in I
(1)
(1)
(1)
/
ADMSK3
RCEN
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
2
R/W-0
R/W-0
ADD3
C™ MODE) – CONTINUED
(1)
/
ADMSK2
PEN
R/W-0
2
R/W-0
ADD2
C module is active, these bits
© 2005 Microchip Technology Inc.
(1)
/
x = Bit is unknown
x = Bit is unknown
ADMSK1
RSEN
R/W-0
R/W-0
ADD1
(1)
/
2
C Master
SEN
R/W-0
R/W-0
ADD0
bit 0
bit 0
(1)
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