PIC18LF2221-I/SP Microchip Technology, PIC18LF2221-I/SP Datasheet - Page 65

• Manufacturer Part Number: PIC18LF2221-I/SP
• Description: IC PIC MCU FLASH 2KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2221-I/SP

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 5-2:
© 2005 Microchip Technology Inc.
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
INDF2
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
Indirect Data Memory Address Pointer 1 Low Byte
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
Indirect Data Memory Address Pointer 2 Low Byte
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0); otherwise, RE3 reads as
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
STKFUL
GIE/GIEH
INT2IP
RBPU
Bit 7
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321)
(6)
STKUNF
PEIE/GIEL
INTEDG0
INT1IP
Bit 6
—
—
—
—
—
—
—
—
(6)
Holding Register for PC<21:16>
INTEDG1
TMR0IE
bit 21
Bit 5
—
—
—
—
—
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Advance Information
INTEDG2
INT0IE
INT2IE
Bit 4
SP4
—
—
—
—
N
Indirect Data Memory Address Pointer 0 High Byte
Indirect Data Memory Address Pointer 1 High Byte
Bank Select Register
Indirect Data Memory Address Pointer 2 High Byte
INT1IE
RBIE
Bit 3
SP3
OV
—
PIC18F4321 FAMILY
TMR0IP
TMR0IF
Bit 2
SP2
—
Z
‘
0
’
. Reset values are shown for 40/44-pin devices;
INT0IF
INT2IF
Bit 1
SP1
DC
—
INT1IF
RBIF
RBIP
Bit 0
SP0
C
‘
0
’
. See Section 2.6.4 “PLL in
---0 0000
0000 0000
0000 0000
00-0 0000
--00 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
---- 0000
xxxx xxxx
xxxx xxxx
---- 0000
xxxx xxxx
---- 0000
---- 0000
xxxx xxxx
---x xxxx
DS39689A-page 63
POR, BOR
Value on
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
‘
0
’
. This bit is
Details on
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49, 54
49, 76
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49, 68
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50, 68
50, 68
50, 59
50, 68
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50, 66
49