PIC18F2331-E/SP Microchip Technology, PIC18F2331-E/SP Datasheet
PIC18F2331-E/SP
Specifications of PIC18F2331-E/SP
Related parts for PIC18F2331-E/SP
PIC18F2331-E/SP Summary of contents
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... PIC18F2331/2431/4331/4431 Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D © 2007 Microchip Technology Inc. Data Sheet 28/40/44-Pin Enhanced Flash Preliminary DS39616C ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F4431 16384 8192 768 © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Power-Managed Modes: • Run: CPU on, Peripherals on • Idle: CPU off, Peripherals on • Sleep: CPU off, Peripherals off • Idle mode Currents Down to 5.8 μA, Typical • Sleep Current Down to 0.1 μA, Typical • ...
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... RA4/AN4/CAP3/QEB OSC2/CLKO/RA6 Note 1: Low-Voltage Programming must be enabled. DS39616C-page -/CAP1/INDX 1 21 REF +/CAP2/QEA 2 20 REF 3 19 PIC18F2331 PIC18F2431 OSC1/CLKI/RA7 Preliminary RB7/KBI3/PGD RB6/KBI2/PGC (1) RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RC7/RX/DT/SDO RC6/TX/CK/SS RC5/INT2/SCK/SCL RC4/INT1/SDI/SDA RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RC7/RX/DT/SDO © 2007 Microchip Technology Inc. ...
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... Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: Low-Voltage Programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ...
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... PIC18F2331/2431/4331/4431 Pin Diagrams (Continued) 44-Pin TQFP RC7/RX/DT/SDO (3) RD4/FLTA (4) RD5/PWM4 RD6/PWM6 RD7/PWM7 RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: Low-Voltage Programming must be enabled. 3: RD4 is the alternate pin for FLTA. ...
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... Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: Low-Voltage Programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 OSC2/CLKO/RA6 1 33 OSC1/CLKI/RA7 2 ...
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... PIC18F2331/2431/4331/4431 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Oscillator Configurations ............................................................................................................................................................ 23 3.0 Power-Managed Modes ............................................................................................................................................................. 33 4.0 Reset .......................................................................................................................................................................................... 47 5.0 Memory Organization ................................................................................................................................................................. 59 6.0 Flash Program Memory .............................................................................................................................................................. 77 7.0 Data EEPROM Memory ............................................................................................................................................................. 87 8 Hardware Multiplier............................................................................................................................................................ 91 9.0 Interrupts .................................................................................................................................................................................... 93 10.0 I/O Ports ................................................................................................................................................................................... 109 11.0 Timer0 Module ......................................................................................................................................................................... 135 12.0 Timer1 Module ......................................................................................................................................................................... 139 13 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Preliminary DS39616C-page 7 ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 8 Preliminary © 2007 Microchip Technology Inc. ...
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... MULTIPLE OSCILLATOR OPTIONS family AND FEATURES All of the devices in the PIC18F2331/2431/4331/4431 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators. ...
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... PIC18F2331/2431/4331/4431 1.2 Other Special Features • Memory Endurance: The enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 100 years. • ...
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... PIC18F2331/4331 PIC18F2431/4431). 2. A/D channels (5 for PIC18F2331/2431 devices, 9 for PIC18F4331/4431 devices). 3. I/O ports (3 bidirectional ports on PIC18F2331/ 2431 devices, PIC18F4331/4431 devices). All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3 ...
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... PIC18F2331/2431/4331/4431 FIGURE 1-1: PIC18F2331/2431 BLOCK DIAGRAM Table Pointer<21> 21 inc/dec logic PCLATU Address Latch Program PCU Memory Program Counter Data Latch 16 Table Latch 8 ROM Latch Instruction Decode & Control OSC2/CLKO Timing OSC1/CLKI Generation Start-up Timer T1OSI T1OSO 4X PLL Precision Band Gap Reference ...
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... RD4 is the alternate pin for FLTA. 3: RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL, respectively. 4: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Data Bus<8> Data Latch 8 8 Data RAM (768 bytes) Address Latch ...
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... PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS Pin Number Pin Name SPDIP, SOIC MCLR/V /RE3 1 PP MCLR V PP RE3 OSC1/CLKI/RA7 9 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 OSC2 CLKO RA6 RA0/AN0 2 RA0 AN0 RA1/AN1 3 RA1 AN1 RA2/AN2/V -/CAP1/INDX 4 REF RA2 AN2 V - REF CAP1 INDX ...
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... TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, SOIC RB0/PWM0 21 RB0 PWM0 RB1/PWM1 22 RB1 PWM1 RB2/PWM2 23 RB2 PWM2 RB3/PWM3 24 RB3 PWM3 RB4/KBI0/PWM5 25 RB4 KBI0 PWM5 RB5/KBI1/PWM4/PGM 26 RB5 KBI1 PWM4 PGM RB6/KBI2/PGC 27 RB6 KBI2 PGC RB7/KBI3/PGD 28 RB7 KBI3 ...
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... PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, SOIC RC0/T1OSO/T1CKI 11 RC0 T1OSO T1CKI RC1/T1OSI/CCP2/FLTA 12 RC1 T1OSI CCP2 FLTA RC2/CCP1/FLTB 13 RC2 CCP1 FLTB RC3/T0CKI/T5CKI/INT0 14 RC3 T0CKI T5CKI INT0 RC4/INT1/SDI/SDA 15 RC4 INT1 SDI SDA RC5/INT2/SCK/SCL 16 RC5 INT2 SCK ...
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... RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type 18 Master Clear (input) or programming voltage (input). ...
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... PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RA0/AN0 2 19 RA0 AN0 RA1/AN1 3 20 RA1 AN1 RA2/AN2/V -/CAP1 REF INDX RA2 AN2 V - REF CAP1 INDX RA3/AN3 REF CAP2/QEA RA3 AN3 V + REF CAP2 QEA RA4/AN4/CAP3/QEB ...
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... RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RC0/T1OSO/T1CKI 15 32 RC0 T1OSO T1CKI RC1/T1OSI/CCP2 FLTA RC1 T1OSI CCP2 FLTA RC2/CCP1/FLTB 17 36 RC2 CCP1 FLTB RC3/T0CKI/T5CKI INT0 RC3 (1) T0CKI (1) T5CKI INT0 RC4/INT1/SDI/SDA 23 42 RC4 INT1 ...
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... RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTD is a bidirectional I/O port. 38 ...
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... PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RE0/AN6 8 25 RE0 AN6 RE1/AN7 9 26 RE1 AN7 RE2/AN8 10 27 RE2 AN8 — 12, 13, 33, 34 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F2331/2431/4331/4431 devices can be operated in 10 different oscillator modes. The user can program the Configuration bits FOSC3:FOSC0 in Configuration Register 1H to select one of these 10 modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL Enabled 5 ...
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... PIC18F2331/2431/4331/4431 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq kHz 33 pF 200 kHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... OSC1/CLKI Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.5 RC Oscillator For timing insensitive applications, the RC and RCIO device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R ) and capacitor (C EXT operating temperature ...
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... PIC18F2331/2431/4331/4431 2.6 Internal Oscillator Block The PIC18F2331/2431/4331/4431 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC MHz clock source, which can be used to directly drive the system clock ...
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... Center frequency. Oscillator module is running at the calibrated frequency. 111111 • • • • 100000 = Minimum frequency © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ...
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... Like previous PIC18 devices, the PIC18F2331/2431/ 4331/4431 devices include a feature that allows the sys- tem clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2331/ 2431/4331/4431 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various power-managed operating modes ...
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... FIGURE 2-8: PIC18F2331/2431/4331/4431 CLOCK DIAGRAM Primary Oscillator OSC2 Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI OSCCON<6:4> Internal Oscillator Block INTRC Source © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 CONFIG1H <3:0> HSPLL 4 x PLL LP, XT, HS, RC, EC Clock Source Option for other Modules OSCCON< ...
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... PIC18F2331/2431/4331/4431 REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IDLEN: Idle Enable bit 1 = Idle mode enabled; CPU core is not clocked in power-managed modes 0 = Run mode enabled; CPU core is clocked in power-managed modes ...
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... OSCILLATOR TRANSITIONS The PIC18F2331/2431/4331/4431 devices contain circuitry to prevent clocking “glitches” when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 32 Preliminary © 2007 Microchip Technology Inc. ...
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... POWER-MANAGED MODES The PIC18F2331/2431/4331/4431 devices offer a total of six operating modes for more efficient power management (see Table 3-1). These operating modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • ...
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... PIC18F2331/2431/4331/4431 3.1.2 ENTERING POWER-MANAGED MODES In general, entry, exit and switching between power- managed clock sources requires clock source switching. In each case, the sequence of events is the same. Any change in the power-managed mode begins with loading the OSCCON register and executing a SLEEP instruction. The SCS1:SCS0 bits select one of three power-managed clock sources ...
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... Not clocked (not running) Any Run mode Secondary or INTOSC multiplexer 3.2 Sleep Mode The power-managed Sleep mode in the PIC18F2331/ 2431/4331/4431 devices is identical to that offered in ® all other PIC microcontrollers entered by clearing the IDLEN and SCS1:SCS0 bits (this is the Reset state) and executing the SLEEP instruction. This shuts down the primary oscillator and the OSTS bit is cleared (see Figure 3-1) ...
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... PIC18F2331/2431/4331/4431 FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE OSC1 CPU Clock Peripheral Clock Sleep Program PC Counter FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) OSC1 (1) T OST PLL Clock Output CPU Clock Peripheral Clock Program PC Counter Wake Event Note 1024 T ...
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... Program PC Counter Wake Event © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately 10 μs is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wake- up, the OSTS bit remains set ...
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... PIC18F2331/2431/4331/4431 3.3.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered by setting the Idle bit, modifying SCS1:SCS0 = 01 and executing a SLEEP instruction. When the clock source is switched (see Figure 3-5) to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set ...
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... OST OSC PLL © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 instruction was executed, and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source ...
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... PIC18F2331/2431/4331/4431 3.4 Run Modes If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits. While these operating modes may not afford the power conservation of Idle or Sleep modes, they do allow the device to continue executing instructions by using a lower frequency clock source ...
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... CPU Clock Peripheral Clock Program PC Counter © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: Caution should be used when modifying a single IRCF bit possible to select a higher clock speed than is supported by the low V Improper device operation may result if the V If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
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... PIC18F2331/2431/4331/4431 3.4.4 EXIT TO IDLE MODE An exit from a power-managed Run mode to its corre- sponding Idle mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS or T1RUN). ...
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... Execution continues during the INTOSC stabilization period. 5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other required delays (see Section 3.3 “Idle Modes”). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Clock Ready Status bit Mode Exit Delay (OSCCON) ...
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... PIC18F2331/2431/4331/4431 3.5.2 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration Register 1H) becomes ready. At that time, the OSTS bit is set and the device begins executing code. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 22.3 “ ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.6.3 EXAMPLE A CCP module can use free-running Timer1, clocked by the internal oscillator block and an external event with a known period (i ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 46 Preliminary © 2007 Microchip Technology Inc. ...
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... RESET The PIC18F2331/2431/4331/4431 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “ ...
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... Electrical Overstress (EOS). DS39616C-page 48 4.2 Power-up Timer (PWRT) The Power-up Timer (PWRT) of the PIC18F2331/2431/ 4331/4431 devices is an 11-bit counter, which uses the INTRC source as the clock input. This yields a count of 2048 x 32 μs = 65.6 ms. While the PWRT is counting, the device is held in Reset. ...
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... When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bring- ing MCLR high will begin execution immediately (Figure 4-5) ...
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... PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices TOSU 2331 2431 4331 4431 TOSH 2331 2431 4331 4431 TOSL 2331 2431 4331 4431 STKPTR 2331 2431 4331 4431 PCLATU 2331 2431 4331 4431 PCLATH 2331 2431 4331 4431 ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices ADRESH 2331 2431 4331 4431 ADRESL 2331 2431 4331 4431 ADCON0 2331 2431 4331 4431 ADCON1 2331 2431 4331 4431 ADCON2 2331 2431 4331 4431 ADCON3 2331 2431 4331 4431 ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PTCON0 2331 2431 4331 4431 PTCON1 2331 2431 4331 4431 PTMRL 2331 2431 4331 4431 PTMRH 2331 2431 4331 4431 PTPERL 2331 2431 4331 4431 PTPERH 2331 2431 4331 4431 ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F2331/2431/4331/4431 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 , V RISE > PWRT T OST T PWRT T OST T ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 58 Preliminary © 2007 Microchip Technology Inc. ...
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... Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all ‘0’s (a NOP instruction). The PIC18F2331/4331 devices each have 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. The PIC18F2431/4431 devices each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions ...
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... PIC18F2331/2431/4331/4431 5.2 Return Address Stack The return address stack allows any combination program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. ...
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... POP instruction. The POP instruc- tion discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘ ...
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... PIC18F2331/2431/4331/4431 5.3 Fast Register Stack A “fast return” option is available for interrupts. A Fast Register Stack is provided for the STATUS, WREG and BSR registers and are only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.6 Instruction Flow/Pipelining An “ ...
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... ADDWF DS39616C-page 64 5.7.1 TWO-WORD INSTRUCTIONS PIC18F2331/2431/4331/4431 devices have four two- word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is decoded as a NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction ...
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... Figure 5-6 shows the data memory organization for the PIC18F2331/2431/4331/4431 devices. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR< ...
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... PIC18F2331/2431/4331/4431 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2331/2431/4331/4431 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 1110 Bank 14 00h = 1111 Bank 15 FFh DS39616C-page 66 Data Memory Map 000h Access RAM 05Fh 060h GPR ...
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... Table 5-1 and Table 5-2. The SFRs can be classified into two sets; those asso- ciated with the “core” function and those related to the peripheral functions. Those registers related to the TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2331/2431/4331/4431 DEVICES Address Name Address Name ...
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... Reset. 5: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 reads ‘0’. This bit is read-only. ...
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... Reset. 5: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 reads ‘0’. This bit is read-only. ...
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... Reset. 5: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 reads ‘0’. This bit is read-only. ...
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... Reset. 5: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 reads ‘0’. This bit is read-only. ...
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... PIC18F2331/2431/4331/4431 5.10 Access Bank The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. This data memory region can be used for: • Intermediate computational values • Local variables of subroutines • ...
Page 75
... FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 If INDF0, INDF1 or INDF2 are read indirectly via a FSRn, all ‘0’s are read (Zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the Status bits are not affected ...
Page 76
... PIC18F2331/2431/4331/4431 FIGURE 5-8: INDIRECT ADDRESSING OPERATION Instruction Executed Opcode BSR<3:0> Instruction Fetched Opcode FIGURE 5-9: INDIRECT ADDRESSING 3 11 Note 1: For register file map detail, see Table 5-1. DS39616C-page 74 0h RAM Address FFFh 12 File Address = access of an Indirect Addressing register File FSRn ...
Page 77
... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged) ...
Page 78
... PIC18F2331/2431/4331/4431 5.14 RCON Register The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. REGISTER 5-3: RCON: RESET CONTROL REGISTER ...
Page 79
... Note 1: Table Pointer points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...
Page 80
... PIC18F2331/2431/4331/4431 FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
Page 81
... RD is cleared in hardware. The RD bit can only be set (not cleared) in soft- ware. RD bit cannot be set when EEPGD = 1 Read completed Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
Page 82
... PIC18F2331/2431/4331/4431 6.2.2 TABLAT TABLE LATCH REGISTER – The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR TABLE POINTER – REGISTER The Table Pointer (TBLPTR) addresses a byte within the program memory ...
Page 83
... MOVFW TABLAT MOVWF WORD_ODD © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
Page 84
... PIC18F2331/2431/4331/4431 6.4 Erasing Flash Program Memory The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control can larger blocks of program memory be bulk erased. Word erase in Flash memory is not supported. ...
Page 85
... CFGS bit to access program memory; - set WREN bit to enable byte writes. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes, because only the holding registers are written ...
Page 86
... PIC18F2331/2431/4331/4431 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVFW TABLAT MOVWF POSTINC0 DECFSZ COUNTER GOTO READ_BLOCK ...
Page 87
... Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; disable interrupts ; required sequence ; write 55H ; write 0AAH ...
Page 88
... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 86 Preliminary © 2007 Microchip Technology Inc. ...
Page 89
... The EECON2 register is used exclusively in the memory write and erase sequences. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, oper- ations will access the data EEPROM memory. When set, program memory is accessed ...
Page 90
... PIC18F2331/2431/4331/4431 REGISTER 7-1: EECON1: FLASH PROGRAM/DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 EEPGD CFGS — bit 7 Legend Settable only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory ...
Page 91
... SLEEP BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
Page 92
... PIC18F2331/2431/4331/4431 7.7 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write opera- tions are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 22.0 “ ...
Page 93
... HARDWARE MULTIPLIER 8.1 Introduction hardware multiplier is included in the ALU of the PIC18F2331/2431/4331/4431 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit Product register pair (PRODH:PRODL). The multiplier does not affect any flags in the STATUS register ...
Page 94
... PIC18F2331/2431/4331/4431 Example 8-3 shows the sequence unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = (ARG1H • ARG2H • (ARG1H • ARG2L • 2 (ARG1L • ARG2H • 2 (ARG1L • ...
Page 95
... Individual interrupts can be disabled through their corresponding enable bits. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are devices have ...
Page 96
... PIC18F2331/2431/4331/4431 FIGURE 9-1: INTERRUPT LOGIC TXIF TXIE TXIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation TXIF TXIE TXIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts DS39616C-page 94 TMR0IF TMR0IE TMR0IP RBIF RBIE ...
Page 97
... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit ...
Page 98
... PIC18F2331/2431/4331/4431 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 99
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 U-0 ...
Page 100
... PIC18F2331/2431/4331/4431 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) Registers (PIR1, PIR2 and PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 101
... No TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Not used in this mode. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 U-0 R/W-0 EEIF — LVDIF U = Unimplemented bit, read as ‘0’ ...
Page 102
... PIC18F2331/2431/4331/4431 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIF: PWM Time Base Interrupt bit 1 = PWM time base matched the value in the PTPER registers. Interrupt is issued according to the postscaler settings ...
Page 103
... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘ ...
Page 104
... PIC18F2331/2431/4331/4431 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 U-0 OSCFIE — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-5 Unimplemented: Read as ‘0’ ...
Page 105
... IC1IE: IC1 Interrupt Enable bit 1 = IC1 interrupt enabled 0 = IC1 interrupt disabled bit 0 TMR5IE: Timer5 Interrupt Enable bit 1 = Timer5 interrupt enabled 0 = Timer5 interrupt disabled © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 PTIE IC3DRIE IC2QEIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 106
... PIC18F2331/2431/4331/4431 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (IPR1, IPR2 and IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 107
... High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-1 U-0 R/W-1 EEIP — LVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ...
Page 108
... PIC18F2331/2431/4331/4431 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIP: PWM Time Base Interrupt Priority bit 1 = High priority ...
Page 109
... For details of bit operation, see Register 5-3. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 5-3. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-3. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...
Page 110
... PIC18F2331/2431/4331/4431 9.6 INTx Pin Interrupts External interrupts on the RC3/INT0, RC4/INT1 and RC5/INT2 pins are edge-triggered; either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RC3/INT0 pin, the corresponding flag bit, INTxIF is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE ...
Page 111
... PORT Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 112
... PIC18F2331/2431/4331/4431 FIGURE 10-2: BLOCK DIAGRAM OF RA0 RD LATA Data Bus LATA or PORTA CK Q Data Latch TRISA CK Q Analog Input TRIS Latch Mode RD TRISA PORTA To A/D Converter FIGURE 10-4: BLOCK DIAGRAM OF RA3:RA2 RD LATA Data Bus LATA or PORTA CK Q Data Latch TRISA CK Q TRIS Latch ...
Page 113
... FIGURE 10-5: BLOCK DIAGRAM OF RA4 Data Bus D WR LATA or PORTA Data Latch D WR TRISA TRIS Latch RD PORTA To A/D Converter To CAP3/QEB Note 1: Open-drain usually available on RA4 has been removed for this device. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RD LATA Analog Input Mode ...
Page 114
... PIC18F2331/2431/4331/4431 FIGURE 10-6: BLOCK DIAGRAM OF RA5 RD LATA Data Bus LATA or PORTA Data Latch TRISA Analog TRIS Latch Input Mode or LVDIN Enabled RD TRISA PORTA To A/D Converter/LVD Module Input FIGURE 10-7: BLOCK DIAGRAM OF RA6 EC/ECIO or RC/RCIO Enable Data Bus RD LATA LATA or PORTA CK Q Data Latch ...
Page 115
... RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: ANS5 through ANS8 are available only on the PIC18F4331/4431 devices. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Buffer TTL Input/output or analog input. TTL Input/output or analog input ...
Page 116
... PIC18F2331/2431/4331/4431 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 117
... PORT/PWM Select PWM0 Data RD LATB Data Bus D WR LATB or PORTB CK Data Latch D WR TRISB CK TRIS Latch RD TRISB RD PORTB Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Preliminary ...
Page 118
... PIC18F2331/2431/4331/4431 FIGURE 10-10: BLOCK DIAGRAM OF RB4 (1) RBPU PORT/PWM Select PWM5 Data RD LATB Data Bus D WR LATB or PORTB CK Data Latch D WR TRISB CK TRIS Latch RD TRISB RD LATB RD PORTB Set RBIF From other RB7:RB4 pins Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). ...
Page 119
... PWM4 Data Data Bus PORTB CK Q Data Latch TRISB CK TRIS Latch RD TRISB RD PORTB Set RBIF From other RB7:RB4 pins LVP Configuration Bit Low-Voltage Programming Enable 0 = Only High-Voltage Programming © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RBPU TTL Input Buffer PORTB EN Q3 Enable ICSP™ ...
Page 120
... PIC18F2331/2431/4331/4431 FIGURE 10-12: BLOCK DIAGRAM OF RB7:RB6 Enable Debug or ICSP™ RBPU RD LATB Data Bus D WR LATB or PORTB CK Data Latch D WR TRISB CK TRIS Latch RD TRISB RD PORTB Enable Debug or ICSP™ Set RBIF From other RB7:RB4 pins (2) (3) PGC /PGD Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). ...
Page 121
... INT1IP — Legend unknown unchanged value depends on condition unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Function (1) Input/output pin or PCPWM output PWM0. Internal software programmable weak pull-up. (1) Input/output pin or PCPWM output PWM1. Internal software programmable weak pull-up ...
Page 122
... PIC18F2331/2431/4331/4431 10.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
Page 123
... Note 1: FLTA input is multiplexed with RC1 and RD4 using FLTAMX Configuration bit in CONFIG3H register. FIGURE 10-15: BLOCK DIAGRAM OF RC2 PORT/CCP1 Select CCP1 Data Out RD LATC Data Bus D WR LATC or PORTC CK Data Latch D WR TRISC CK TRIS Latch RD TRISC RD PORTC CCP1 Input/FLTB Input © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ...
Page 124
... PIC18F2331/2431/4331/4431 FIGURE 10-16: BLOCK DIAGRAM OF RC3 RD LATC Data Bus LATC or PORTC CK Q Data Latch TRISC CK Q TRIS Latch RD TRISC RD PORTC T0CKI/T5CKI Input Note 1: The T0CKI/T5CKI bit is multiplexed with RD0 when the EXCLKMX is enabled (= 1) in the Configuration register. FIGURE 10-17: BLOCK DIAGRAM OF RC4 PORT/SSP Mode & ...
Page 125
... Note 1: SCK/SCL are multiplexed on RD3 and RC5 using SSPMX bit in the Configuration register. FIGURE 10-19: BLOCK DIAGRAM OF RC6 EUSART Select TX Data Out/CK RD LATC Data Bus D WR LATC or PORTC CK Data Latch D WR TRISC CK TRIS Latch RD TRISC EUSART Select RD PORTC CK Input SS Input © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Schmitt Trigger ...
Page 126
... PIC18F2331/2431/4331/4431 FIGURE 10-20: BLOCK DIAGRAM OF RC7 (1) EUSART Select DT Data Out PORT/(SSPEN * SPI Mode) Select (2) SDO Data Out RD LATC Data Bus D WR LATC or PORTC CK Data Latch D WR TRISC CK TRIS Latch RD TRISC (1) EUSART Select RD PORTC RX/DT Data Input Note 1: EUSART is in Synchronous Master Transmission mode only (SYNC = 2: SDO must have its TRISC bit cleared in order to be able to drive RC7 ...
Page 127
... INTCON3 INT2IP INT1IP — Legend unknown unchanged unimplemented, read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. Compare2 output/PWM output when CCP2Mx bit is disabled or FLTA input. ST Input/output port pin, Capture1 input/Compare1 output/PWM1 output or FLTB input ...
Page 128
... PIC18F2331/2431/4331/4431 10.4 PORTD, TRISD and LATD Registers Note: PORTD is only available on PIC18F4331/ 4431 devices. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 129
... TRIS Latch RD TRISD RD PORTD FIGURE 10-23: BLOCK DIAGRAM OF RD4 RD LATD Data Bus LATD or PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD FLTA Input Note 1: FLTAMX is located in the Configuration register, CONFIG3H. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Schmitt Trigger Schmitt ...
Page 130
... PIC18F2331/2431/4331/4431 FIGURE 10-24: BLOCK DIAGRAM OF RD3 2 I C™ Mode PORT/SSPEN & SSPMX Select SCK/SCL Data Out RD LATD Data Bus LATD or PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD SCK or SCL Input Note 1: SCK/SCL are multiplexed on RD3 and RC5 using the SSPMX bit in the Configuration register. ...
Page 131
... Note 1: The SDO output is multiplexed by the SSPMX bit in the Configuration register. FIGURE 10-27: BLOCK DIAGRAM OF RD0 RD LATD Data Bus D WR LATD or PORTD CK Data Latch D WR TRISD CK TRIS Latch RD TRISD RD PORTD T0CKI/T5CKI Input Note 1: T0CKI/T5CKI are multiplexed by the SSPMX bit in the Configuration register. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ...
Page 132
... PIC18F2331/2431/4331/4431 TABLE 10-7: PORTD FUNCTIONS Name Bit # Buffer Type RD0/T0CKI/T5CKI bit 0 ST RD1/SDO bit 1 ST RD2/SDI/SDA bit 2 ST RD3/SCK/SCL bit 3 ST (1) RD4/FLTA bit 4 ST (2) RD5/PWM4 bit 5 ST RD6/PWM6 bit 6 ST RD7/PWM7 bit 7 ST Legend Schmitt Trigger input, TTL = TTL input Note 1: RD4 is the alternate pin for FLTA ...
Page 133
... ANSEL1, 0 MOVLW 0x03 MOVWF TRISE 10.5.1 PORTE IN 28-PIN DEVICES For PIC18F2331/2431 devices, PORTE is only available when master clear functionality is disabled (CONFIG3H<7> = 0). In these cases, PORTE is a single bit, input-only port comprised of RE3 only. The pin operates as previously described. Preliminary /RE3 input ...
Page 134
... PIC18F2331/2431/4331/4431 FIGURE 10-28: BLOCK DIAGRAM OF RE2:RE0 RD LATE Data Bus D WR LATE or PORTE CK Data Latch D WR TRISE CK TRIS Latch RD TRISE RD PORTE To A/D Converter Channel AN6, AN7 or AN8 FIGURE 10-29: BLOCK DIAGRAM OF RE3 MCLR/V PP MCLRE Data Bus RD TRISE Schmitt Trigger RD LATE Latch PORTE ...
Page 135
... Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0). 2: ANS5 through ANS8 are available only on PIC18F4331/4431 devices. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 U-0 R/W-1 — — TRISE2 U = Unimplemented bit, read as ‘ ...
Page 136
... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 134 Preliminary © 2007 Microchip Technology Inc. ...
Page 137
... Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 138
... PIC18F2331/2431/4331/4431 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE OSC T0CKI Pin 1 T0SE T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE F /4 OSC 0 T0CKI Pin 1 Programmable Prescaler T0SE ...
Page 139
... Legend unknown unchanged. Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol (i.e., it can be changed “ ...
Page 140
... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 138 Preliminary © 2007 Microchip Technology Inc. ...
Page 141
... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 142
... PIC18F2331/2431/4331/4431 12.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the Timer1 Clock Select bit, TMR1CS (T1CON<1>). FIGURE 12-1: TIMER1 BLOCK DIAGRAM TMR1IF Overflow TMR1 Interrupt Flag Bit TMR1H ...
Page 143
... Microchip Technology Inc. PIC18F2331/2431/4331/4431 12.3 Timer1 Oscillator Layout Considerations The Timer1 oscillator for PIC18F2331/2431/4331/4431 devices incorporates an additional low-power feature. When this option is selected, it allows the oscillator to automatically reduce its power consumption when the microcontroller is in Sleep mode. During normal device operation, the oscillator draws full current ...
Page 144
... PIC18F2331/2431/4331/4431 12.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in Timer1 Interrupt Flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 Interrupt Enable bit, TMR1IE (PIE1< ...
Page 145
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...
Page 146
... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 144 Preliminary © 2007 Microchip Technology Inc. ...
Page 147
... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset ...
Page 148
... PIC18F2331/2431/4331/4431 13.2 Timer2 Interrupt The Timer2 module has an 8-bit Period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: ...
Page 149
... TMR5ON: Timer5 On bit 1 = Timer5 enabled 0 = Timer5 disabled Note 1: These bits are not implemented on PIC18F2331/2431 devices and read as ‘0’. 2: For Timer5 to operate during Sleep mode, T5SYNC must be set. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Timer5 is a general purpose timer/counter that incor- porates additional features for use with the Motion Feedback Module (see Section 16.0 “ ...
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... PIC18F2331/2431/4331/4431 FIGURE 14-1: TIMER5 BLOCK DIAGRAM (16-BIT READ/WRITE MODE SHOWN) Noise Filter T5CKI F /4 OSC Internal Clock TMR5CS T5PS1:T5PS0 T5SYNC TMR5ON Special Event Trigger Input 1 from IC1 Timer5 Reset 0 (external) Set TMR5IF Special Event Trigger Output 14.1 Timer5 Operation Timer5 combines two 8-bit registers to function as a 16-bit timer. The TMR5L register is the actual low byte of the timer ...
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... Reset is present on the Timer5 Reset input. (See Section 14.7 “Timer5 Special Event Trigger Reset Input” for additional information). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 14.2 16-Bit Read/Write and Write Modes As noted, the actual high byte of the Timer5 register pair is mapped to TMR5H, which serves as a buffer. ...
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... PIC18F2331/2431/4331/4431 14.4 Noise Filter The Timer5 module includes an optional input noise filter, designed to reduce spurious signals in noisy operating environments. The filter ensures that the input is not permitted to change until a stable value has been registered for three consecutive sampling clock cycles. The noise filter is part of the input filter network associ- ated with the Motion Feedback Module (see Section 16.0 “ ...
Page 153
... RESEN T5MOD CAP1CON — CAP1REN — DFLTCON — FLT4EN FLT3EN Legend unknown unchanged unimplemented. Shaded cells are not used by the Timer5 module. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF PTIP IC3DRIP IC2QEIP IC1IP PTIE ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 152 Preliminary © 2007 Microchip Technology Inc. ...
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... Compare mode; initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode; Special Event Trigger (CCPxIF bit is set) 11xx = PWM mode © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 15-1: CCP Mode Capture Compare PWM 15 ...
Page 156
... PIC18F2331/2431/4331/4431 15.3 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: • every falling edge • every rising edge • every 4th rising edge • every 16th rising edge The event is selected by control bits, CCP1M3:CCP1M0 (CCP1CON< ...
Page 157
... Output Enable Q RC1/CCP2 Pin TRISC<1> Output Enable © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.4.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro- nized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. ...
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... PIC18F2331/2431/4331/4431 TABLE 15-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Name Bit 7 Bit 6 Bit 5 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 — ADIF RCIF PIE1 — ADIE RCIE IPR1 — ADIP RCIP TRISC PORTC Data Direction Register TMR1L Timer1 Register Low Byte TMR1H ...
Page 159
... PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.5.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation: EQUATION 15-1: PWM Period = [(PR2 • 4 • T PWM frequency is defined as 1/[PWM period] ...
Page 160
... PIC18F2331/2431/4331/4431 The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The ...
Page 161
... Utilizes Input Capture 1 Logic (IC1) • High and Low Velocity Support © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Many of the features for the IC and QEI submodules are fully programmable, creating a flexible peripheral structure that can accommodate a wide range of in-system uses. An overview of the available features is presented in Table 16-1 ...
Page 162
... PIC18F2331/2431/4331/4431 FIGURE 16-1: MOTION FEEDBACK MODULE BLOCK DIAGRAM Special Event Trigger Reset Timer Reset Filter T5CKI Filter CAP3/QEB Filter CAP2/QEA Filter CAP1/INDX T CY Clock Divider CHGIF DS39616C-page 160 TMR5 Reset Control Timer5 Input Capture Logic TMR5<15:0> IC3 IC2 IC1 Postscaler QEB ...
Page 163
... Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active. 2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Input Channel 1 (IC1) includes a Special Event Trigger that can be configured for use in Velocity Mea- surement mode ...
Page 164
... PIC18F2331/2431/4331/4431 FIGURE 16-3: INPUT CAPTURE BLOCK DIAGRAM FOR IC2 AND IC3 CAP2/3 Pin Prescaler Noise Filter FLTCK<2:0> CAP1M<3:0> Q Clocks Note 1: IC2 and IC3 are denoted and 3. 2: CAP2BUF is enabled as POSCNT when QEI mode is active. 3: CAP3BUF is enabled as MAXCNT when QEI mode is active. ...
Page 165
... Capture mode, every falling edge 0000 = Input Capture x (ICx) off Note 1: Special Event Trigger is only available on CAP1. For CAP2 and CAP3, this configuration is unused. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: Throughout this section, references to registers, registers and bit names that may be asso- ...
Page 166
... PIC18F2331/2431/4331/4431 When in Counter mode, the counter must be configured as the synchronous (T5SYNC = 0). When configured in Asynchronous mode, the IC module will not work properly. Note 1: Input capture prescalers (cleared) when the input capture module is disabled (CAPxM = 0000). 2: When the Input Capture mode is changed without first disabling the module and ...
Page 167
... Measurement mode active on each falling edge detected. 5: TMR5 Reset pulse is activated on the capture edge. CAP1REN bit has no bearing in this mode. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Timer5 is always reset on the edge when the measurement is first initiated. For example, when the measurement is based on the falling to rising edge, Timer5 is first reset on the falling edge and the timer value is captured on the rising edge thereafter ...
Page 168
... PIC18F2331/2431/4331/4431 16.1.3.1 Pulse-Width Measurement Timing Pulse-width measurement accuracy can only be ensured when the pulse-width high and low present on the CAPx input exceeds one T clock cycle. The CY limitations depend on the mode selected: • When CAPxM3:CAPxM0 = 0110 (rising to falling edge delay), the CAPx input high pulse width ...
Page 169
... Reset on the CAP1 input. In order for the Special Event Trigger Reset to work as the Reset trigger to Timer5, IC1 must be configured in the Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.1.6 TIMER5 RESET Every input capture trigger can optionally reset (TMR5) ...
Page 170
... PIC18F2331/2431/4331/4431 16.1.8 SPECIAL EVENT TRIGGER (CAP1 ONLY) The Special Event Trigger mode (CAP1M3:CAP1M0 = 1110 or 1111) enables the Special Event Trigger signal. The trigger signal can be used as the Special Event Trigger Reset input to TMR5, resetting the timer when the specific event happens on IC1 ...
Page 171
... CAP2/QEA Filter CAP1/INDX © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The QEI control logic detects the leading edge on the QEA or QEB phase input pins and generates the count pulse, which is sent to the position counter logic. It also samples the index input signal (INDX) and generates the direction of the rotation signal (up/down) and the velocity event signals ...
Page 172
... PIC18F2331/2431/4331/4431 16.2.1 QEI CONFIGURATION The QEI module shares its input pins with the Input Capture (IC) module. The inputs are mutually exclusive; only the IC module or the QEI module (but not both) can be enabled at one time. Also, because the IC and QEI are multiplexed to the same input pins, the programmable noise filters can be dedicated to one module only ...
Page 173
... Like QEI x2 mode, the position counter can be reset by an input on the pin (QEIM2:QEIM0 = 101 the period match event (QEIM2:QEIM0 = 010). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.2.3 QEI OPERATION The Position Counter register pair (POSCNTH: POSCNTL) acts as an integrator, whose value is propor- tional to the position of the sensor rotor that corresponds to the number of active edges detected ...
Page 174
... PIC18F2331/2431/4331/4431 16.2.3.3 Reset and Update Events The position counter will continue to increment or dec- rement until one of the following events takes place. The type of event and the direction of rotation when it happens determines if a register Reset or update occurs index pulse is detected on the INDX input (QEIM2:QEIM0 = 001) ...
Page 175
... POSCNT = 0 (when decrementing), which occurs on the next QEA falling edge. 3: IC2QEIF is generated on Q4 rising edge. 4: Position counter is loaded with ‘0’ (which is a rollover event in this case) on POSCNT = MAXCNT. 5: Position counter is loaded with MAXCNT value (1527h) on underflow. 6: IC2QEIF must be cleared in software. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ( QEI /16 ...
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... PIC18F2331/2431/4331/4431 FIGURE 16-11: QEI MODULE RESET TIMING WITH THE INDEX INPUT Forward Note 2 QEA QEB Count (+/-) + (1) POSCNT MAXCNT MAXCNT = 1527 INDX IC2QEIF UP/DOWN Q4 Q1 Position Counter Load Note 1: POSCNT register is shown in QEI x4 Update mode (POSCNT increments on every rising and every falling edge of QEA and QEB input signals). 2: When INDX Reset pulse is detected, POSCNT is reset to ‘ ...
Page 177
... QEB QEA CAP2/QEA INDX CAP1/INDX © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.2.6.1 Velocity Event Timing The event pulses are reduced by a fixed ratio by the velocity pulse divider. The divider is useful for high-speed measurements where the velocity events happen frequently. By producing a single output pulse for a given number of input event pulses, the counter can track larger pulse counts (i ...
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... PIC18F2331/2431/4331/4431 FIGURE 16-13: VELOCITY MEASUREMENT TIMING QEA QEB vel_out velcap (2) TMR5 (2) VELR Old Value (3) cnt_reset (4) IC1IF CAP1REN Instr. BCF T5CON, VELM BCF PIE2, IC1IE Execution Note 1: Timing shown is for QEIM<2:0> = 101, 110 or 111 (x4 Update mode enabled) and the velocity postscaler divide ratio is set to divide by 4 (PDEC< ...
Page 179
... Noise filter output enables are functional in both QEI and IC Operating modes. Note: The Noise Filter is intended for random high-frequency filtering and not continuous high-frequency filtering. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 programmed by the FLTCK2:FLTCK0 Configuration bits used as the clock reference to the clock CY divider block ...
Page 180
... PIC18F2331/2431/4331/4431 FIGURE 16-14: NOISE FILTER TIMING DIAGRAM (CLOCK DIVIDER = 1: (1) CAP1/INDX Pin (input to filter) (2) CAP1/INDX Input (output from filter Note 1: Only CAP1/INDX pin input is shown for simplicity. Similar event timing occurs on CAP2/QEA and CAP3/QEB pins. 2: Noise filtering occurs in shaded portions of CAP1 input. ...
Page 181
... Shaded cells are not used by the Motion Feedback Module. Note 1: Register name and function determined by which submodule is selected (IC/QEI, respectively). See Section 16.1.10 “Other Operating Modes” for more information. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE ...
Page 182
... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 180 Preliminary © 2007 Microchip Technology Inc. ...
Page 183
... Debug mode. The Power Control PWM module supports three PWM generators and PIC18F2331/2431 devices, and four generators and eight channels on PIC18F4331/4431 devices. A simpli- fied block diagram of the module is shown in Figure 17-1. Figure 17-2 and Figure 17-3 show how ...
Page 184
... SEVTCMP Note 1: Only PWM Generator 3 is shown in detail. The other generators are identical; their details are omitted for clarity. 2: PWM Generator 3 and its logic, PWM channels 6 and 7, and FLTB and its associated logic are not implemented on PIC18F2331/2431 devices. DS39616C-page 182 (1) PWM Generator #3 ...
Page 185
... In Complementary modes, the even PWM pins must always be the complement of the corresponding odd PWM pin. For example, PWM0 will be the complement of PWM1, PWM2 will be the complement of PWM3 and so on. The dead-time © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 V DD Dead-Band Generator V ...
Page 186
... PIC18F2331/2431/4331/4431 17.1 Control Registers The operation of the PWM module is controlled by a total of 22 registers. Eight of these are used to configure the features of the module: • PWM Timer Control Register 0 (PTCON0) • PWM Timer Control Register 1 (PTCON1) • PWM Control Register 0 (PWMCON0) • PWM Control Register 1 (PWMCON1) • ...
Page 187
... The PWM time base can be configured for four different modes of operation: • Free-Running mode • Single-Shot mode • Continuous Up/Down Count mode • Continuous Up/Down Count mode with interrupts for double updates © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PTMR Clock Timer Reset Up/Down Zero Match Timer Direction PTDIR ...
Page 188
... PIC18F2331/2431/4331/4431 REGISTER 17-1: PTCON0: PWM TIMER CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 PTOPS3 PTOPS2 PTOPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 PTOPS3:PTOPS0: PWM Time Base Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale ...
Page 189
... When PWMEN2:PWMEN0 = 101, PWM<5:0> outputs are enabled for PIC18F2331/2431 devices; PWM<7:0> outputs are enabled for PIC18F4331/4431 devices. When PWMEN2:PWMEN0 = 111, PWM outputs 1, 3 and 5 are enabled in PIC18F2331/2431 devices; PWM outputs and 7 are enabled in PIC18F4331/4431 devices. 3: Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. ...
Page 190
... PIC18F2331/2431/4331/4431 REGISTER 17-4: PWMCON1: PWM CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 SEVOPS3 SEVOPS2 SEVOPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 SEVOPS3:SEVOPS0: PWM Special Event Trigger Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale ...
Page 191
... PTMR FFEh PTMR_INT_REQ PTIF bit Note 1: PWM Time Base Period register, PTPER, is loaded with the value FFFh for this example. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.3.5 PWM TIME BASE POSTSCALER The match output of PTMR can optionally MHz postscaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate an interrupt ...
Page 192
... PIC18F2331/2431/4331/4431 17.4.2 INTERRUPTS IN SINGLE-SHOT MODE When the PWM time base is in the Single-Shot mode (PTMOD<1:0> = 01), an interrupt event is generated when a match with the PTPER register occurs. The PWM Time Base register (PTMR) is reset to zero on the following input clock edge and the PTEN bit is cleared ...
Page 193
... PWM TIME BASE INTERRUPT, CONTINUOUS UP/DOWN COUNT MODE A: PRESCALER = 1 OSC PTMR 002h PTDIR bit PTMR_INT_REQ 1 1 PTIF bit B: PRESCALER = 1 002h PTMR PTDIR bit 1 1 PTMR_INT_REQ PTIF bit Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 001h 000h 001h 000h 1 1 Preliminary ...
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... PIC18F2331/2431/4331/4431 17.4.4 INTERRUPTS IN DOUBLE UPDATE MODE This mode is available in Continuous Up/Down Count mode. In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero and each time the PTMR matches with PTPER register. Figure 17-8 shows the interrupts in Continuous Up/Down Count mode with double updates ...
Page 195
... EQUATION 17-3: PWM FREQUENCY 1 PWM Frequency = PWM Period © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 17-4: Resolution = The PWM resolutions and frequencies are shown for a selection of execution speeds and PTPER values in Table 17-2 ...
Page 196
... PIC18F2331/2431/4331/4431 FIGURE 17-9: PWM PERIOD BUFFER UPDATES IN FREE-RUNNING MODE New PTPER Value = 007 Old PTPER Value = 004 1 0 FIGURE 17-10: PWM PERIOD BUFFER UPDATES IN CONTINUOUS UP/DOWN COUNT MODE New PTPER Value = 007 Old PTPER Value = 004 1 0 DS39616C-page 194 Period Value Loaded from PTPER Register ...
Page 197
... duty cycle match occurs on Q4 © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The value in each Duty Cycle register determines the amount of time that the PWM output is in the active state. The upper 12 bits of PDCx holds the actual duty cycle value from PTMRH/L< ...
Page 198
... PIC18F2331/2431/4331/4431 17.6.2 DUTY CYCLE REGISTER BUFFERS The four PWM Duty Cycle double-buffered to allow glitchless updates of the PWM outputs. For each duty cycle block, there is a Duty Cycle Buffer register that is accessible by the user and a second Duty Cycle register that holds the actual compare value used in the present PWM period ...
Page 199
... PWM period © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 New Values Written to Duty Cycle Buffer inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register ...
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... PIC18F2331/2431/4331/4431 17.6.5 COMPLEMENTARY PWM OPERATION The Complementary mode of PWM operation is useful to drive one or more power switches in half-bridge configuration as shown in Figure 17-16. This inverter topology is typical for a 3-phase induction motor, brushless DC motor or a 3-phase Uninterruptible Power Supply (UPS) control applications. Each upper/lower power switch pair is fed by a complementary PWM signal ...