PIC18F2431-E/SO Microchip Technology, PIC18F2431-E/SO Datasheet - Page 163

• Manufacturer Part Number: PIC18F2431-E/SO
• Description: IC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2431-E/SO

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 24
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16.1
The Input Capture (IC) submodule implements the
following features:
• Three channels of independent input capture
• Edge-Trigger, Period or Pulse-Width
• Programmable prescaler on every input capture
• Special Event Trigger output (IC1 only)
• Selectable noise filters on each capture input
FIGURE 16-2:
© 2007 Microchip Technology Inc.
(16-bits/channel) on the CAP1, CAP2 and CAP3
pins
Measurement Operating modes for each channel
channel
Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active.
CAP1 Pin
velcap
Input Capture
2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal.
(2)
FLTCK<2:0>
VELM
1
0
MUX
Noise
Filter
3
INPUT CAPTURE BLOCK DIAGRAM FOR IC1
Prescaler
1, 4, 16
CAP1M<3:0> Q Clocks
Q Clocks
4
Interrupt
Decode
Select
Mode
Reset/
Clock/
Logic
and
CAP1M<3:0>
PIC18F2331/2431/4331/4431
Preliminary
First Event
Reset
CAP1BUF_clk
Input Channel 1 (IC1) includes a Special Event
surement mode. Its block diagram is shown in
Figure 16-2. IC2 and IC3 are similar, but lack the
measurement logic. A representative block diagram is
shown in Figure 16-3. Please note that the time base
is Timer5.
Trigger that can be configured for use in Velocity Mea-
Special Event Trigger features or additional velocity
Event Trigger
Special
IC1_TR
Reset
IC1IF
Timer5 Logic
CAP1BUF/VELR
TMR5
Control
Timer
Reset
DS39616C-page 161
(1)
Reset
Control
Timer5 Reset
Clock
Reset