PIC18F1330-I/SO Microchip Technology, PIC18F1330-I/SO Datasheet - Page 119

• Manufacturer Part Number: PIC18F1330-I/SO
• Description: IC PIC MCU FLASH 4KX16 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1330-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 14-2:
FIGURE 14-3:
This module contains three duty cycle generators,
numbered 0 through 2. The module has six PWM
output pins, numbered 0 through 5. The six PWM
outputs are grouped into output pairs of even and odd
numbered outputs. In Complementary modes, the
even PWM pins must always be the complement of the
corresponding odd PWM pins. For example, PWM0 will
be the complement of PWM1 and PWM2 will be the
complement of PWM3. The dead-time generator
 2009 Microchip Technology Inc.
Note:
Fault A pin
Fault A pin
PWM Duty Cycle Register
In the Complementary mode, the even channel cannot be forced active by a Fault or override event when the odd channel is
active. The even channel is always the complement of the odd channel and is inactive, with dead time inserted, before the odd
channel is driven to its active state.
Duty Cycle Comparator
Channel Override Values
Fault Override Values
Fault Pin Assignment
PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, COMPLEMENTARY MODE
PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, INDEPENDENT MODE
Channel Override Values
PWM Duty Cycle Register
Duty Cycle Comparator
Fault Override Values
Fault Pin Assignment
Logic
Logic
V
DD
Dead-Band
Generator
inserts an OFF period called “dead time” between the
going OFF of one pin to the going ON of the
complementary pin of the paired pins. This is to prevent
damage to the power switching devices that will be
connected to the PWM output pins.
The time base for the PWM module is provided by its
own 12-bit timer, which also incorporates selectable
prescaler and postscaler options.
V
V
DD
DD
PIC18F1230/1330
HPOL
LPOL
HPOL
LPOL
DS39758D-page 119
PWM1
PWM0
PWM1
PWM0