PIC18F1330-I/SO Microchip Technology, PIC18F1330-I/SO Datasheet - Page 49

• Manufacturer Part Number: PIC18F1330-I/SO
• Description: IC PIC MCU FLASH 4KX16 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1330-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 5-4:
 2009 Microchip Technology Inc.
EEADR
EEDATA
EECON2
EECON1
IPR3
PIR3
PIE3
IPIR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
PTCON0
PTCON1
PTMRL
PTMRH
PTPERL
PTPERH
TRISB
TRISA
PDC0L
PDC0H
PDC1L
PDC1H
PDC2L
PDC2H
FLTCONFIG
LATB
LATA
SEVTCMPL
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition
Note 1:
Register
2:
3:
4:
5:
6:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 5-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
1230
Applicable
Devices
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
1330
Brown-out Reset
Power-on Reset,
0000 0000
0000 0000
0000 0000
xx-0 x000
---1 ----
---0 ----
---0 ----
1--1 -1--
0--0 -0--
0--0 -0--
-111 1111
-000 0000
-000 0000
00-0 0000
0000 0000
00-- ----
0000 0000
---- 0000
1111 1111
---- 1111
1111 1111
1111 1111
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
--00 0000
0--- -000
xxxx xxxx
xxxx xxxx
0000 0000
(5)
(5)
RESET Instruction,
MCLR Resets,
0000 0000
0000 0000
0000 0000
uu-0 u000
---1 ----
---0 ----
---0 ----
1--1 -1--
0--0 -0--
0--0 -0--
-111 1111
-000 0000
-000 0000
00-0 0000
uuuu uuuu
00-- ----
0000 0000
---- 0000
1111 1111
---- 1111
1111 1111
1111 1111
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
--00 0000
0--- -000
uuuu uuuu
uuuu uuuu
0000 0000
Stack Resets
WDT Reset,
PIC18F1230/1330
(5)
(5)
Wake-up via WDT
uuuu uuuu
uuuu uuuu
0000 0000
uu-0 u000
---u ----
---u ----
---u ----
u--u -u--
u--u -u--
u--u -u--
-uuu uuuu
-uuu uuuu
-uuu uuuu
uu-u uuuu
uuuu uuuu
uu-- ----
uuuu uuuu
---- uuuu
uuuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
--uu uuuu
u--- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
or Interrupt
DS39758D-page 49
(1)
(1)
(5)
(5)