DSPIC33FJ12MC202-I/ML Microchip Technology, DSPIC33FJ12MC202-I/ML Datasheet - Page 62

• Manufacturer Part Number: DSPIC33FJ12MC202-I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ12MC201/202
5.2
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
V
has elapsed. The delay T
device bias circuits become stable.
The device supply voltage characteristics must meet
the
requirements
Section 23.0 “Electrical Characteristics” for details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
5.3
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the V
(V
cuit keeps the device in Reset until V
FIGURE 5-3:
DS70265C-page 60
DD
DD
crosses the V
< V
SYSRST
SYSRST
SYSRST
specified
BOR
Power-on Reset (POR)
Brown-out Reset (BOR) and
Power-up timer (PWRT)
V
V
V
DD
DD
DD
) for proper device operation. The BOR cir-
to
starting
V
POR
DD
generate the POR. Refer to
dips before PWRT expires
BROWN-OUT SITUATIONS
threshold and the delay T
voltage
POR
ensures the internal
and
DD
DD
crosses the
rise
is too low
POR
rate
Preliminary
T
BOR
+ T
T
T
PWRT
BOR
BOR
V
delay T
becomes stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The device will not run at full speed after a BOR as the
V
operation. The PWRT provides power-up time delay
(T
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (T
the
(FPWRT<2:0>)
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 20.0 “Special
Features” for further details.
Figure 5-3 shows the typical brown-out scenarios. The
reset delay (T
rises above the V
BOR
DD
+ T
PWRT
+ T
PWRT
should rise to acceptable levels for full-speed
PWRT
threshold and the delay T
Power-on
) to ensure that the system power supplies have
BOR
BOR
ensures the voltage regulator output
BOR
bits
+ T
Reset
PWRT
trip point
in
© 2008 Microchip Technology Inc.
) is initiated each time V
the
V
V
PWRT
V
Timer
BOR
BOR
BOR
BOR
POR
) is programmed by
has elapsed. The
Value
Configuration
Select
DD