PIC18F2420-I/SO Microchip Technology, PIC18F2420-I/SO Datasheet - Page 176
![IC MCU FLASH 8KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F2420-I/SO
Manufacturer Part Number
PIC18F2420-I/SO
Description
IC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2420-IML.pdf
(412 pages)
2.PIC18F2420-IML.pdf
(16 pages)
3.PIC18F2420-IML.pdf
(8 pages)
4.PIC18F2420-IML.pdf
(6 pages)
5.PIC18F2420-IML.pdf
(8 pages)
6.PIC18F2420-IML.pdf
(4 pages)
7.PIC18F4420-IP.pdf
(390 pages)
Specifications of PIC18F2420-I/SO
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI/I2C/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2420-I/SO
Manufacturer:
MICROCHIP
Quantity:
1 560
Part Number:
PIC18F2420-I/SO
Manufacturer:
NXP/恩智浦
Quantity:
20 000
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PIC18F2420/2520/4420/4520
17.4.2
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON<5>).
The SSPCON1 register allows control of the I
operation. Four mode selection bits (SSPCON<3:0>)
allow one of the following I
• I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC bits. To ensure proper
operation of the module, pull-up resistors must be
provided externally to the SCL and SDA pins.
17.4.3
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
• The overflow bit, SSPOV (SSPCON<6>), was set
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
MSSP module, are shown in timing parameter 100 and
parameter 101.
DS39631A-page 174
2
C specification, as well as the requirement of the
Stop bit interrupts enabled
Stop bit interrupts enabled
Idle
before the transfer was received.
before the transfer was received.
2
2
2
2
2
2
C Master mode, clock = (F
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address) with Start and
C Slave mode (10-bit address) with Start and
C Firmware Controlled Master mode, slave is
2
C Slave mode hardware will always generate an
OPERATION
SLAVE MODE
2
C mode with the SSPEN bit set,
2
C modes to be selected:
OSC
/4) x (SSPADD + 1)
Preliminary
2
C
17.4.3.1
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1.
2.
3.
4.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with steps 7 through 9 for the slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated, if enabled) on the
falling edge of the ninth SCL pulse.
Receive first (high) byte of address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
Addressing
2004 Microchip Technology Inc.
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