PIC18F2420-I/SO Microchip Technology, PIC18F2420-I/SO Datasheet - Page 182
![IC MCU FLASH 8KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F2420-I/SO
Manufacturer Part Number
PIC18F2420-I/SO
Description
IC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2420-IML.pdf
(412 pages)
2.PIC18F2420-IML.pdf
(16 pages)
3.PIC18F2420-IML.pdf
(8 pages)
4.PIC18F2420-IML.pdf
(6 pages)
5.PIC18F2420-IML.pdf
(8 pages)
6.PIC18F2420-IML.pdf
(4 pages)
7.PIC18F4420-IP.pdf
(390 pages)
Specifications of PIC18F2420-I/SO
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI/I2C/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2420-I/SO
Manufacturer:
MICROCHIP
Quantity:
1 560
Part Number:
PIC18F2420-I/SO
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- PIC18F2420-IML PDF datasheet
- PIC18F2420-IML PDF datasheet #2
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- PIC18F2420-IML PDF datasheet #4
- PIC18F2420-IML PDF datasheet #5
- PIC18F2420-IML PDF datasheet #6
- PIC18F4420-IP PDF datasheet #7
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- Download datasheet (8Mb)
PIC18F2420/2520/4420/4520
17.4.4
Both 7-bit and 10-bit Slave modes implement
automatic clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
17.4.4.1
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit in the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 17-13).
17.4.4.2
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
DS39631A-page 180
Note:
Note 1: If the user reads the contents of the
2: The CKP bit can be set in software
CLOCK STRETCHING
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Clock Stretching for 7-bit Slave
Receive Mode (SEN =
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
1
)
Preliminary
17.4.4.3
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 17-9).
17.4.4.4
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 17-11).
Note 1: If the user loads the contents of SSPBUF,
2: The CKP bit can be set in software
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
regardless of the state of the BF bit.
Clock Stretching for 7-bit Slave
Transmit Mode
Clock Stretching for 10-bit Slave
Transmit Mode
2004 Microchip Technology Inc.
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