ATMEGA128A-MUR Atmel, ATMEGA128A-MUR Datasheet - Page 139
![MCU AVR 128K FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128A-MUR
Manufacturer Part Number
ATMEGA128A-MUR
Description
MCU AVR 128K FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.11.7
15.11.8
15.11.9
15.11.10 OCR1BH and OCR1BL - Output Compare Register 1 B
8151H–AVR–02/11
TCNT1H and TCNT1L - Timer/Counter1
TCNT3H and TCNT3LTimer/Counter3
OCR1AH and OCR1AL - Output Compare Register 1 A
• Bit 4:0 – Reserved
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when TCCRnC is written.
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This Temporary Register is shared by all the other 16-bit registers.
bit Registers” on page 115.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
OCR1B[15:8]
OCR1A[15:8]
TCNT1[15:8]
TCNT3[15:8]
OCR1B[7:0]
OCR1A[7:0]
TCNT1[7:0]
TCNT3[7:0]
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
ATmega128A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
See “Accessing 16-
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
OCR1BH
OCR1BL
OCR1AH
OCR1AL
TCNT1H
TCNT1L
TCNT3H
TCNT3L
139
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