ATMEGA128A-MUR Atmel, ATMEGA128A-MUR Datasheet - Page 66
![MCU AVR 128K FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128A-MUR
Manufacturer Part Number
ATMEGA128A-MUR
Description
MCU AVR 128K FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12.2
12.2.1
8151H–AVR–02/11
Ports as General Digital I/O
Configuring the Pin
Functions” on page
nate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as General Digital I/O.
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O port pin, here generically called Pxn.
Figure 12-2. General Digital I/O
Note:
Each port pin consists of three Register bits: DDxn, PORTxn, and PINxn. As shown in
Description” on page
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
Pxn
1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
71. Refer to the individual module sections for a full description of the alter-
:
86, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
(1)
SLEEP
SYNCHRONIZER
WDx:
RDx:
WPx:
RRx:
RPx:
D
L
Q
Q
D
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
PINxn
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
Figure 12-2
DDxn
CLR
CLR
ATmega128A
D
D
PUD
WDx
RDx
WPx
RPx
clk
RRx
shows a func-
I/O
I/O
, SLEEP,
“Register
66
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