ATMEGA128A-MUR Atmel, ATMEGA128A-MUR Datasheet - Page 263
![MCU AVR 128K FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128A-MUR
Manufacturer Part Number
ATMEGA128A-MUR
Description
MCU AVR 128K FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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24.13.5
8151H–AVR–02/11
Scanning the Analog Comparator
Figure 24-9. Boundary-scan Cells for Oscillators and Clock Options
Figure 24-10.
Table 24-3.
Notes:
The relevant Comparator signals regarding Boundary-scan are shown in
Boundary-scan cell from
described in
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Enable signal
EXTCLKEN
OSCON
RCOSCEN
OSC32EN
TOSKON
From Digital Logic
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
the Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided. The INTCAP fuses are not supported
in the scan-chain, so the boundary scan chain can not make a XTAL Oscillator requiring inter-
nal capacitors to run unless the fuse is correctly programmed.
Table
Table 24-3
lators with XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.
Scan Signals for the Oscillators
Previous
From
Cell
Scanned Clock Line
EXTCLK (XTAL1)
OSCCK
RCCK
OSC32CK
TOSCK
ShiftDR
24-4.
0
1
ClockDR
summaries the scan registers for the external clock pin XTAL1, oscil-
Figure 24-12
D
UpdateDR
Q
Next
Cell
To
D
G
Q
EXTEST
is attached to each of these signals. The signals are
0
1
Clock Option
External Clock
External Crystal
External Ceramic Resonator
External RC
Low Freq. External Crystal
32kHz Timer Oscillator
XTAL1/TOSC1
(1)(2)(3)
ENABLE
Oscillator
XTAL2/TOSC2
OUTPUT
Previous
From
Cell
ShiftDR
0
1
ClockDR
ATmega128A
Scanned Clock Line
when not Used
D
FF1
Q
Figure
next
cell
To
To System Logic
0
0
1
0
0
24-11. The
263
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