AT32UC3B1128-AUR Atmel, AT32UC3B1128-AUR Datasheet - Page 243
![MCU AVR32 128K FLASH 48-TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3B1128-AUR
Manufacturer Part Number
AT32UC3B1128-AUR
Description
MCU AVR32 128K FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B1128-AUR
Package / Case
48-TQFP, 48-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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19.13.6
19.13.6.1
Figure 19-27. Clock Synchronization in Read Mode
Notes:
32059J–12/2010
TWI_THR
TXCOMP
SVREAD
SCLWS
SVACC
TXRDY
TWCK
1. TXRDY is reset when data has been written in the TH to the shift register and set when this data has been acknowledged or
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
3. SCLWS is automatically set when the clock synchronization mechanism is started.
Clock Synchronization
non acknowledged.
SADR.
Clock Synchronization in Read Mode
1
2
S
S
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
As soon as a START is detected
SADR
In both read and write modes, it may happen that THR/RHR buffer is not filled /emptied before
the emission/reception of a new character. In this case, to avoid sending/receiving undesired
data, a clock stretching mechanism is implemented.
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition
was not detected. It is tied low until the shift register is loaded.
Figure 19-27 on page 243
DATA0
DATA0
R
Write THR
A
1
DATA0
A
describes the clock synchronization in Read mode.
DATA1
DATA1
CLOCK is tied low by the TWI
as long as THR is empty
A
XXXXXXX
2
DATA2
DATA2
Ack or Nack from the master
NA
AT32UC3B
S
243
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