AT32UC3B1128-AUR Atmel, AT32UC3B1128-AUR Datasheet - Page 528
![MCU AVR32 128K FLASH 48-TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3B1128-AUR
Manufacturer Part Number
AT32UC3B1128-AUR
Description
MCU AVR32 128K FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B1128-AUR
Package / Case
48-TQFP, 48-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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24.6
24.6.1
32059J–12/2010
Functional Description
PWM Clock Generator
The PWM macrocell is primarily composed of a clock generator module and
Figure 24-2. Functional View of the Clock Generator Block Diagram
Caution: Before using the PWM macrocell, the programmer must ensure that the PWM clock in
the Power Manager is enabled.
The PWM macrocell master clock, CLK_PWM, is divided in the clock generator module to pro-
vide different clocks available for all channels. Each channel can independently select one of the
– Clocked by the system clock, CLK_PWM, the clock generator module provides 13
– Each channel can independently choose one of the clock generator outputs.
– Each channel generates an output waveform with attributes that can be defined
clocks.
independently for each channel through the user interface registers.
CLK_PWM
modulo n
Counter
PREA
PREB
MR
MR
Divider A
Divider B
DIVA
DIVB
CLK_PWM/32
CLK_PWM/2
CLK_PWM/16
CLK_PWM/64
CLK_PWM/128
CLK_PWM/256
CLK_PWM/512
CLK_PWM/1024
CLK_PWM
CLK_PWM/4
CLK_PWM/8
clk B
clk A
AT32UC3B
7
channels.
528
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