PIC18F87K22-I/PTRSL Microchip Technology, PIC18F87K22-I/PTRSL Datasheet - Page 185

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PIC18F87K22-I/PTRSL

Manufacturer Part Number
PIC18F87K22-I/PTRSL
Description
MCU PIC 128K FLASH XLP 80TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F87K22-I/PTRSL

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F87K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
12.10 PORTJ, TRISJ and
PORTJ is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISJ and LATJ.
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
When the external memory interface is enabled, all of
the PORTJ pins function as control outputs for the inter-
face. This occurs automatically when the interface is
enabled
(MEMCON<7>). The TRISJ bits are also overridden.
 2010 Microchip Technology Inc.
Note:
Note:
LATJ Registers
by
PORTJ is available only on 80-pin devices.
These pins are configured as digital inputs
on any device Reset.
clearing
the
EBDIS
control
Preliminary
bit
PIC18F87K22 FAMILY
Each of the PORTJ pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit RJPU (PADCFG1<5>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
EXAMPLE 12-9:
CLRF
CLRF
MOVLW
MOVWF
PORTJ
LATJ
0CFh
TRISJ
; Initialize PORTJ by
; clearing output latches
; Alternate method
; to clear output latches
; Value used to
; initialize data
; direction
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
INITIALIZING PORTJ
DS39960B-page 185

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