PIC24FJ64GA010-I/PT Microchip Technology, PIC24FJ64GA010-I/PT Datasheet - Page 11

• Manufacturer Part Number: PIC24FJ64GA010-I/PT
• Description: IC PIC MCU FLASH 32KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA010-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 100-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 84
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240011, AC164127, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164333 - MODULE SKT FOR PM3 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

30. Module: SPI (Slave Mode)
31. Module: Oscillator (Two-Speed Start-up)
32. Module: Core (Reset)
© 2009 Microchip Technology Inc.
In SPI Slave mode (MSTEN = 0), with the slave
select option enabled (SSEN = 1), the peripheral
may accept transfers regardless of the SSx pin
state. The received data in SSPxBUF will be
accurate but not intended for the device.
Work around
If the Slave select option is required (e.g., the
device is one of multiple SPI slave nodes on an
SPI network), two potential work arounds exist:
1. Configure the port associated with SSx to an
2. Read the pin associated with SSx after a trans-
Affected Silicon Revisions
The Two-Speed Start-up feature may not be
available on exit from Sleep mode with the IESO
bit (Internal External Switchover mode) enabled.
Upon wake-up, the device will wait for the clock
source used prior to entering Sleep mode to
become ready.
Work around
None.
Affected Silicon Revisions
The CLKDIV register Reset value is incorrect. The
register will reset with unimplemented bits equal to
‘1’ for all Resets.
Work around
Mask out unimplemented bits to maintain software
compatibility with future device revisions.
Affected Silicon Revisions
A2
A2
A2
X
X
X
input and periodically read the PORT register. If
the pin is read ‘0’, disable the SPI peripheral
(SPIEN = 0). Enable the peripheral (SPIEN = 1)
if the pin is read as a logic ‘1’.
fer is complete, indicated by the SPIxF bit
being set. If the port pin is read as a digital ‘1’,
read SSPxBUF and discard the contents.
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
C1
C1
C1
C2
C2
C2
PIC24FJ128GA010 FAMILY
33. Module: Core (Traps)
34. Module: Core (Resets)
35. Module: I/O Ports
If a clock failure occurs when the device is in Idle
mode, the oscillator failure trap does not vector to
the Trap Service Routine. Instead, the device will
simply wake-up from Idle mode and continue code
execution if the Fail-Safe Clock Monitor (FSCM) is
enabled.
Work around
Whenever the device wakes up from Idle (assuming
the FSCM is enabled), the user software should
check the status of the OSCFAIL bit (INTCON1<1>)
to determine whether a clock failure occurred and
then perform an appropriate clock switch operation.
Affected Silicon Revisions
On a Brown-out Reset, both the BOR and POR
bits may be set. This may cause the Brown-out
Reset condition to be indistinguishable from the
Power-on Reset.
Work around
None.
Affected Silicon Revisions
During Power-on Reset (POR), the device may
drive the OSCO/CLKO/RC15 pin as a clock out
output for approximately 20 μs. During this time,
the pin will be driven high and low rather than
being set to high-impedance. This may cause
issues on designs that use the pin as a general
purpose I/O. Designs should be reviewed to
ensure that their intended operation will not be
disrupted if the pin is driven during POR.
Work around
None.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
C1
C1
C1
C2
C2
C2
DS80471A-page 11