PIC24FJ64GA010-I/PT Microchip Technology, PIC24FJ64GA010-I/PT Datasheet - Page 15

• Manufacturer Part Number: PIC24FJ64GA010-I/PT
• Description: IC PIC MCU FLASH 32KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA010-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 100-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 84
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240011, AC164127, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164333 - MODULE SKT FOR PM3 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

51. Module: UART (UERIF Interrupt)
52. Module: UART (FIFO Error Flags)
53. Module: UART
© 2009 Microchip Technology Inc.
The UART error interrupt may not occur, or occur
at an incorrect time, if multiple errors occur during
a short period of time.
Work around
Read the error flags in the UxSTA register when-
ever a byte is received to verify the error status. In
most cases, these bits will be correct, even if the
UART error interrupt fails to occur. For possible
exceptions, refer to Errata # 52.
Affected Silicon Revisions
Under certain circumstances, the PERR and
FERR error bits may not be correct for all bytes in
the receive FIFO. This has only been observed
when both of the following conditions are met:
• the UART receive interrupt is set to occur when
• more than 2 bytes with an error are received.
In these cases, only the first two bytes with a parity
or framing error will have the corresponding bits
indicate correctly. The error bits will not be set after
this.
Work around
None.
Affected Silicon Revisions
The UART may not transmit if data is written to
TXxREG before the module is enabled.
Work around
To ensure transmission occurs, always enable the
UART before the buffer is loaded. Use the proce-
dure in Section 16.2 “Transmitting in 8-Bit Data
Mode” or Section 16.3 “Transmitting in 9-Bit
Data Mode” of the device data sheet (DS39747).
Affected Silicon Revisions
A2
A2
A2
X
the FIFO is full or ¾ full (UxSTA<7:6> = 1x);
and
X
X
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
C1
C1
C1
C2
C2
C2
PIC24FJ128GA010 FAMILY
54. Module: I
55. Module: I
Under certain circumstances, a module operating
in Master mode may Acknowledge its own com-
mand addressed to a slave device. This happens
when the following occurs:
• 10-Bit Addressing mode is used (A10M = 1);
• the I
In these cases, the master also Acknowledges the
address command and generates an erroneous I
slave interrupt, as well as the I
Work around
Several options are available:
• When using 10-Bit Addressing mode, make
If this cannot be avoided:
• Clear the A10M bit (I2CxCON<10> = 0) prior to
• Read the ADD10 bit (I2CxSTAT<8>) to check
Affected Silicon Revisions
Under certain circumstances, a module operating
in Slave mode may not respond correctly to some
of the special addresses reserved by the I
protocol. This happens when the following occurs:
• 10-Bit Addressing mode is used (A10M = 1);
• the A<7:1> bits of the slave address
In these cases, the Slave module Acknowledges
the command and triggers an I
does not copy the data into the I2CxRCV register
or set the RBF bit.
Work around
Do not set bits, A<7:1>, of the module’s slave
address equal to ‘1111xxx’ or ‘0000xxx’.
Affected Silicon Revisions
A2
A2
and
address bits (I2CADD<9:8>) as the addressed
slave module.
certain that the master and slave devices do not
share the same 2 MSbs of their addresses.
performing a Master mode transmit.
for a full 10-bit match whenever a slave I
interrupt occurs on the master module.
and
(I2CADD<7:1>) fall into the range of the
reserved 7-bit address ranges: ‘1111xxx’ or
‘0000xxx’.
X
X
2
C master has the same two upper
A3
A3
X
X
2
2
C (Master Mode)
C (Slave Mode)
A4
A4
X
X
C1
C1
C2
C2
2
2
C master interrupt.
C slave interrupt; it
DS80471A-page 15
2
C
2
2
C
C