PIC24FJ64GA010-I/PT Microchip Technology, PIC24FJ64GA010-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC24FJ64GA010-I/PT
• Description: IC PIC MCU FLASH 32KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA010-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 100-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 84
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240011, AC164127, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164333 - MODULE SKT FOR PM3 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 2:
© 2009 Microchip Technology Inc.
SPI
Oscillator
Core
Core
Core
I/O Ports
I
UART
UART
UART
SPI
Output
Compare
CRC
UART
I
I
RTCC
Core
Memory
I/O
RTCC
UART
UART
UART
I
I
Note 1:
2
2
2
2
2
C
C
C
C
C
Module
Only those issues indicated in the last column apply to the current silicon revision.
Two-Speed
Start-up
Reset
Traps
Resets
Slave mode
Auto-Baud
Auto-Baud
PWM mode
IrDA
Instruction
Set
PSV
PORTB
Alarm
UERIF
Interrupt
FIFO Error
Flags
Master mode
Slave mode
Slave mode
SILICON ISSUE SUMMARY (CONTINUED)
Feature
®
—
—
—
—
—
—
—
—
Number
Item
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
Module in Slave mode may ignore SS pin
and receive data anyway.
Two-Speed Start-up failure when IESO is
enabled.
Unimplemented CLKDIV bits reset to ‘1’.
Clock failure trap does not vector as
expected.
BOR and POR flags both set on BOR.
OSCO/CLKO/RC15 driven immediately
following POR.
D/A bit fails to update in Slave mode
transmissions.
Double receive interrupt with auto-baud
reception.
Auto-baud calculation errors causing
transmit or receive failures.
Erroneous sampling and framing errors
when using two Stop bits.
DISSCK does not disable SPI clock.
Single missed compare events under
certain conditions.
Improper VWORD Reset on FIFO overflow.
IR baud clock only available during transmit.
Issues with write operations on I2CxSTAT.
ACKSTAT prematurely cleared in Slave
mode.
Write errors to ALCFGRPT register.
Loop count errors with REPEAT instruction
and R-A-W stalls.
False address error traps at lower
boundary of PSV space.
RB5 as open-drain output stays in
high-impedance state.
Decrement of alarm repeat counter under
certain conditions.
No UERIF flag with multiple errors.
PERR and FERR not correctly set for all
bytes in receive FIFO.
Does not transmit if TxREG is preloaded.
Module may respond to its own master
transmission as a slave under certain
conditions.
Failure to respond correctly to some
reserved addresses in 10-bit mode.
PIC24FJ128GA010 FAMILY
Issue Summary
A2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected Revisions
A3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DS80471A-page 3
C1
X
X
(1)
C2
X
X