ATMEGA32U4-AU Atmel, ATMEGA32U4-AU Datasheet - Page 261

MCU AVR 32K FLASH 16MHZ 44-TQFP

ATMEGA32U4-AU

Manufacturer Part Number
ATMEGA32U4-AU
Description
MCU AVR 32K FLASH 16MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA32U4-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
26
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
2.5KB
# I/os (max)
26
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
26
Eeprom Memory Size
1KB
Ram Memory Size
2.5KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA32U4-16AU
ATMEGA32U4-16AU

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Quantity
Price
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21.10 PAD suspend
7766F–AVR–11/10
EPEN=1
ALLOC=1
The following figure illustrates the allocation and reorganization of the USB memory in a typical
example:
Table 21-1.
Note that:
The next figures illustrates the pad behaviour:
• First, Endpoint 0 to Endpoint 5 are configured, in the growing order. The memory of each is
• Then, the Endpoint 3 is disabled (EPEN=0), but its memory reservation is internally kept by
• Its ALLOC bit is cleared: the Endpoint 4 “slides” down, but the Endpoint 5 does not “slide”.
• Finally, if the firmware chooses to reconfigure the Endpoint 3, with a bigger size. The
• the data of Endpoint 0 are never lost whatever the activation or deactivation of the higher
• Deactivate and reactivate the same Endpoint with the same parameters does not lead to a
• CFGOK is set by hardware even in the case where there is a “conflict” in the memory
• In the “idle” mode, the pad is put in low power consumption mode.
• In the “active” mode, the pad is working.
Free memory
Endpoints
reserved in the DPRAM.
the controller.
controller reserved the memory after the Endpoint 2 memory and automatically “slide” the
Endpoint 4. The Endpoint 5 does not move and a memory conflict appear, in that both
Endpoint 4 and 5 use a common area. The data of those endpoints are potentially lost.
Endpoint. Its data is lost if it is deactivated.
“slide” of the higher endpoints. For those endpoints, the data are preserved.
allocation.
activation
5
4
3
2
1
0
Allocation and reorganization USB memory flow
Endpoint Disable
Free memory
(ALLOC=1)
EPEN=0
5
4
2
1
0
Free its memory
Free memory
Lost memory
(ALLOC=0)
5
4
2
1
0
ATmega16/32U4
3 (bigger size)
Free memory
Activatation
Endpoint
4
2
1
0
5
Conflict
261

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