ATXMEGA32A4-CU Atmel, ATXMEGA32A4-CU Datasheet - Page 138
ATXMEGA32A4-CU
Manufacturer Part Number
ATXMEGA32A4-CU
Description
MCU AVR 32+4 FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA32A4-CU
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
Processor Series
ATXMEGA32x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
36
Number Of Timers
5
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 1 Channel
On-chip Dac
2 bit, 1 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
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Price
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13.12 Multi-configuration
13.13 Virtual Port Registers
13.14 Register Description – Ports
13.14.1
13.14.2
8077H–AVR–12/09
DIR - Data Direction Register
DIRSET - Data Direction Set Register
be visible on the port pin as long as the event last. Normally this is one peripheral clock cycle
only.
MPCMASK can be used to set a bit mask for the pin configuration registers. When setting bit n in
MPCMASK, PINnCTRL is added to the pin configuration mask. During the next write to any of
the port's pin configuration registers, the same value will be written to all the port's pin configura-
tion registers set by the mask. The MPCMASK register is cleared automatically after the write
operation to the pin configuration registers is finished.
Virtual port registers allow for port registers in the extended I/O memory space to be mapped vir-
tually in the I/O memory space. When mapping a port, writing to the virtual port register will be
the same as writing to the real port register. This enables use of I/O memory specific instructions
for bit-manipulation, and the I/O memory specific instructions IN and OUT on port register that
normally resides in the extended I/O memory space. There are four virtual ports, so up to four
ports can be mapped virtually at the same time. The mapped registers are IN, OUT, DIR and
INTFLAGS.
• Bit 7:0 - DIR[7:0]: Data Direction
This register sets the data direction for the individual pins in the port. If DIRn is written to one, pin
n is configured as an output pin. If DIRn is written to zero, pin n is configured as an input pin.
• Bit 7:0 - DIRSET[7:0]: Port Data Direction Set
This register can be used instead of a Read-Modify-Write to set individual pins as output. Writing
a one to a bit will set the corresponding bit in the DIR register. Reading this register will return
the value of the DIR register.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
DIRSET[7:0]
DIR[7:0]
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
XMEGA A
R/W
R/W
0
0
0
0
DIRSET
DIR
138
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