AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 170
AT91SAM7S321-AU
Manufacturer Part Number
AT91SAM7S321-AU
Description
IC ARM7 MCU FLASH 32K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91SAM7S16-MU.pdf
(51 pages)
2.AT91SAM7S16-MU.pdf
(779 pages)
3.AT91SAM7S321-AU.pdf
(600 pages)
Specifications of AT91SAM7S321-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, I2S, SPI, SSC, TWI, UART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
32
Number Of Timers
10 bit
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxx
No. Of I/o's
32
Ram Memory Size
8KB
Cpu Speed
55MHz
No. Of Timers
3
Rohs Compliant
Yes
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (7Mb)
22.5.3.1
22.5.3.2
170
AT91SAM7S Series Preliminary
Enumeration Process
Communication Endpoints
The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are
used by the host operating system to mount the correct driver. On Windows systems, the INF
files contain the correspondence between vendor ID and product ID.
The USB protocol is a master/slave protocol. This is the host that starts the enumeration send-
ing requests to the device through the control endpoint. The device handles standard requests
as defined in the USB Specification.
Table 22-2.
The device also handles some class requests defined in the CDC class.
Table 22-3.
Unhandled requests are STALLed.
There are two communication endpoints and endpoint 0 is used for the enumeration process.
Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint.
SAM-BA Boot commands are sent by the host through the endpoint 1. If required, the mes-
sage is split by the host into several data payloads by the host driver.
If the command requires a response, the host can send IN transactions to pick up the
response.
Request
GET_DESCRIPTOR
SET_ADDRESS
SET_CONFIGURATION
GET_CONFIGURATION
GET_STATUS
SET_FEATURE
CLEAR_FEATURE
Request
SET_LINE_CODING
GET_LINE_CODING
SET_CONTROL_LINE_STATE
Handled Standard Requests
Handled Class Requests
Definition
Returns the current device configuration value.
Sets the device address for all future device access.
Sets the device configuration.
Returns the current device configuration value.
Returns status for the specified recipient.
Used to set or enable a specific feature.
Used to clear or disable a specific feature.
Definition
Configures DTE rate, stop bits, parity and number of
character bits.
Requests current DTE rate, stop bits, parity and number
of character bits.
RS-232 signal used to tell the DCE device the DTE
device is now present.
6175G–ATARM–22-Nov-06
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