AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 246

• Manufacturer Part Number: AT91SAM7S321-AU
• Description: IC ARM7 MCU FLASH 32K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S321-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, I2S, SPI, SSC, TWI, UART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 10 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 32
• Ram Memory Size: 8KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

27.4.7
27.4.8
246
AT91SAM7S Series Preliminary
Chip Identifier
ICE Access Prevention
The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and
DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first
register contains the following fields:
The second register is device-dependent and reads 0 if the bit EXT is 0.
The Debug Unit allows blockage of access to the system through the ARM processor's ICE
interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows
assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1
in this register prevents any activity on the TAP controller.
On standard devices, the FNTRST bit resets to 0 and thus does not prevent ICE access.
This feature is especially useful on custom ROM devices for customers who do not want their
on-chip code to be visible.
• EXT - shows the use of the extension identifier register
• NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size
• ARCH - identifies the set of embedded peripheral
• SRAMSIZ - indicates the size of the embedded SRAM
• EPROC - indicates the embedded ARM processor
• VERSION - gives the revision of the silicon
6175G–ATARM–22-Nov-06