PIC18F2515-I/SP Microchip Technology, PIC18F2515-I/SP Datasheet - Page 253
![IC MCU FLASH 24KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2515-I/SP
Manufacturer Part Number
PIC18F2515-I/SP
Description
IC MCU FLASH 24KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18LF2410-ISO.pdf
(376 pages)
3.PIC18LF2410-ISO.pdf
(8 pages)
4.PIC18F2515-ISO.pdf
(16 pages)
5.PIC18F2515-ISO.pdf
(6 pages)
6.PIC18F2515-ISO.pdf
(8 pages)
Specifications of PIC18F2515-I/SP
Core Size
8-Bit
Program Memory Size
48KB (24K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Ram Memory Size
3968Byte
Cpu Speed
40MHz
No. Of Timers
4
Interface
I2C, SPI, USART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2515-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18LF2410-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18F2515-ISO PDF datasheet #4
- PIC18F2515-ISO PDF datasheet #5
- PIC18F2515-ISO PDF datasheet #6
- Current page: 253 of 376
- Download datasheet (7Mb)
22.5.1
The program memory may be read to or written from
any location using the table read and table write
instructions. The Device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In Normal Execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. The
EBTRn bits control table reads. For a block of user
memory with the EBTRn bit set to ‘0’, a table read
instruction that executes from within that block is
allowed to read. A table read instruction that executes
FIGURE 22-7:
© 2009 Microchip Technology Inc.
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TBLPTR = 0008FFh
PROGRAM MEMORY
CODE PROTECTION
Register Values
PC = 003FFEh
TABLAT register returns a value of ‘0’.
EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
(16-KBYTE AND 32-KBYTE DEVICES)
Program Memory
TBLRD*
from a location outside of that block is not allowed to
read and will result in reading ‘0’s. Figures 22-7
through 22-10 illustrate table write and table read
protection.
Note:
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
PIC18F2X1X/4X1X
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
Configuration Bit Settings
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
DS39636D-page 255
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