PIC18F2515-I/SP Microchip Technology, PIC18F2515-I/SP Datasheet - Page 343
PIC18F2515-I/SP
Manufacturer Part Number
PIC18F2515-I/SP
Description
IC MCU FLASH 24KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18LF2410-ISO.pdf
(376 pages)
3.PIC18LF2410-ISO.pdf
(8 pages)
4.PIC18F2515-ISO.pdf
(16 pages)
5.PIC18F2515-ISO.pdf
(6 pages)
6.PIC18F2515-ISO.pdf
(8 pages)
Specifications of PIC18F2515-I/SP
Core Size
8-Bit
Program Memory Size
48KB (24K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Ram Memory Size
3968Byte
Cpu Speed
40MHz
No. Of Timers
4
Interface
I2C, SPI, USART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2515-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18LF2410-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18F2515-ISO PDF datasheet #4
- PIC18F2515-ISO PDF datasheet #5
- PIC18F2515-ISO PDF datasheet #6
- Current page: 343 of 376
- Download datasheet (7Mb)
TABLE 25-19: I
© 2009 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1:
Param.
No.
2:
Symbol
T
T
T
T
T
T
T
T
T
T
T
C
SU
SU
SU
AA
R
HIGH
LOW
F
HD
HD
BUF
B
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode I
T
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line, T
Standard mode I
SU
:
:
:
:
:
STA
DAT
STO
STA
DAT
:
DAT
2
Clock High Time
Clock Low Time
SDA and SCL Rise
Time
SDA and SCL Fall
Time
Start Condition
Setup Time
Start Condition
Hold Time
Data Input Hold
Time
Data Input Setup
Time
Stop Condition
Setup Time
Output Valid from
Clock
Bus Free Time
Bus Capacitive Loading
C™ BUS DATA REQUIREMENTS (SLAVE MODE)
≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the
2
C bus device can be used in a Standard mode I
2
C bus specification), before the SCL line is released.
Characteristic
100 kHz mode
400 kHz mode
SSP module
100 kHz mode
400 kHz mode
SSP module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
R
max. + T
20 + 0.1 C
20 + 0.1 C
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
SU
0
0
CY
CY
:
DAT
B
B
PIC18F2X1X/4X1X
= 1000 + 250 = 1250 ns (according to the
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus system, but the requirement
Units
pF
μs
μs
μs
μs
ns
ns
ns
ns
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
C
10 to 400 pF
C
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
B
B
is specified to be from
is specified to be from
Conditions
DS39636D-page 345
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