DSPIC33FJ128MC802-I/SO Microchip Technology, DSPIC33FJ128MC802-I/SO Datasheet - Page 288
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DSPIC33FJ128MC802-I/SO
Manufacturer Part Number
DSPIC33FJ128MC802-I/SO
Description
IC DSPIC MCU/DSP 128K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ128MC802-I/SO
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 288 of 436
- Download datasheet (6Mb)
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
23.4
The DAC clock signal clocks the internal logic of the
Audio DAC module. The data sample rate of the Audio
DAC is an integer division of the rate of the DAC clock.
The DAC clock is generated via a clock divider circuit
that accepts an auxiliary clock from the auxiliary
oscillator. The divisor ratio is programmed by clock
FIGURE 23-1:
FIGURE 23-2:
DS70291E-page 288
Note: V
DAC CLOCK
CONTROL
OD
Note 1:
+ = V
Count (DAC1RDAT)
Output (DAC1RN)
Output (DAC1RP)
Negative DAC
DACH
Positive DAC
DAC input
BLOCK DIAGRAM OF AUDIO DIGITAL-TO-ANALOG (DAC) CONVERTER
AUDIO DAC OUTPUT FOR RAMP INPUT (UNSIGNED)
If DAC1RDAT and DAC1LDAT are empty, data will be taken from the DACDFLT register.
- V
V
DACL
0x0000
V
0xFFFF
V
DACFDIV<6:0>
V
DACL
DACL
DACH
DACH
, V
OD
V
V
- = V
DACM
ACLK
DACM
DACL
DAC1RDAT
DAC1LDAT
- V
CLK DIV
DACH
; refer to Audio DAC Module Specifications,
DACDFLT
divider bits (DACFDIV<6:0>) in the DAC Control
register (DAC1CON). The resulting DAC clock must
not exceed 25.6 MHz. If lower sample rates are to be
used, then the DAC filter clock frequency may be
reduced to reduce power consumption. The DAC clock
frequency is 256 times the sampling frequency.
Note 1
Note 1
D/A
D/A
Table
© 2011 Microchip Technology Inc.
31-48, for typical values.
Amp
Amp
Right Channel
Left Channel
DAC1RM
DAC1RP
DAC1RN
DAC1LM
DAC1LP
DAC1LN
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