AT89C51ED2-RLRUM Atmel, AT89C51ED2-RLRUM Datasheet - Page 63
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AT89C51ED2-RLRUM
Manufacturer Part Number
AT89C51ED2-RLRUM
Description
IC MCU FLASH 8051 64K 5V 44-VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.ATWEBDVK-02RC.pdf
(137 pages)
Specifications of AT89C51ED2-RLRUM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Core
8051
Processor Series
AT89x
Data Bus Width
8 bit
Maximum Clock Frequency
60 MHz
Data Ram Size
2 KB
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Mounting Style
SMD/SMT
Interface Type
UART, SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
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16. Serial Port Interface (SPI)
16.1
16.2
16.2.1
16.2.2
4235K–8051–05/08
Features
Signal Description
Master Output Slave Input (MOSI)
Master Input Slave Output (MISO)
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communica-
tion between the MCU and peripheral devices, including other MCUs.
Features of the SPI Module include the following:
Figure 16-1
peripherals. The bus is made of three wires connecting all the devices.
Figure 16-1. SPI Master/Slaves Interconnection
The Master device selects the individual Slave devices by using four pins of a parallel port to
control the four SS pins of the Slave devices.
This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI
line is used to transfer data in series from the Master to the Slave. Therefore, it is an output sig-
nal from the Master, and an input signal to a Slave. A Byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO
line is used to transfer data in series from the Slave to the Master. Therefore, it is an output sig-
nal from the Slave, and an input signal to the Master. A Byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
• Full-duplex, three-wire synchronous transfers
• Master or Slave operation
• Eight programmable Master clock rates
• Serial clock with programmable polarity and phase
• Master Mode fault error flag with MCU interrupt capability
• Write collision flag protection
shows a typical SPI bus configuration using one Master controller and many Slave
Master
Slave 4
MISO
MOSI
SCK
SS
0
1
2
3
VDD
Slave 3
AT89C51RD2/ED2
Slave 1
Slave 2
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