AT89C51ED2-RLRUM Atmel, AT89C51ED2-RLRUM Datasheet - Page 68
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AT89C51ED2-RLRUM
Manufacturer Part Number
AT89C51ED2-RLRUM
Description
IC MCU FLASH 8051 64K 5V 44-VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.ATWEBDVK-02RC.pdf
(137 pages)
Specifications of AT89C51ED2-RLRUM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Core
8051
Processor Series
AT89x
Data Bus Width
8 bit
Maximum Clock Frequency
60 MHz
Data Ram Size
2 KB
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Mounting Style
SMD/SMT
Interface Type
UART, SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
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16.3.3.1
16.3.3.2
16.3.3.3
16.3.3.4
16.3.4
68
AT89C51RD2/ED2
Interrupts
Mode Fault (MODF)
Write Collision (WCOL)
Overrun Condition
SS Error Flag (SSERR)
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is
inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-
master conflict for system control. In this case, the SPI system is affected in the following ways:
When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the
SS signal becomes ’0’.
However, as stated before, for a system with one Master, if the SS pin of the Master device is
pulled low, there is no way that another Master attempts to drive the network. In this case, to
prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register
and therefore making the SS pin as a general-purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed
by a write to the SPCON register. SPEN Control bit may be restored to its original set state after
the MODF bit has been cleared.
A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done
during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an
access to SPDAT.
An overrun condition occurs when the Master device tries to send several data Bytes and the
Slave devise has not cleared the SPIF bit issuing from the previous data Byte transmitted. In this
case, the receiver buffer contains the Byte sent after the SPIF bit was last cleared. A read of the
SPDAT returns this Byte. All others Bytes are lost.
This condition is not detected by the SPI peripheral.
A Synchronous Serial Slave Error occurs when SS goes high before the end of a received data
in slave mode. SSERR does not cause in interruption, this bit is cleared by writing 0 to SPEN bit
(reset of the SPI state machine).
Two SPI status flags can generate a CPU interrupt requests:
Table 16-2.
Flag
SPIF (SP data transfer)
MODF (Mode Fault)
• An SPI receiver/error CPU interrupt request is generated
• The SPEN bit in SPCON is cleared. This disables the SPI
• The MSTR bit in SPCON is cleared
SPI Interrupts
Request
SPI Transmitter Interrupt request
SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)
4235K–8051–05/08