AT32UC3B0256-Z2UR Atmel, AT32UC3B0256-Z2UR Datasheet - Page 17
![MCU AVR32 256K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT32UC3B0256-Z2UR
Manufacturer Part Number
AT32UC3B0256-Z2UR
Description
MCU AVR32 256K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B0256-Z2UR
Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 17 of 680
- Download datasheet (10Mb)
6. Processor and Architecture
6.1
6.2
32059J–12/2010
Features
AVR32 Architecture
Rev: 1.0.0.0
This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the
AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre-
sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical
Reference Manual.
•
•
•
AVR32 is a high-performance 32-bit RISC microprocessor architecture, designed for cost-sensi-
tive embedded applications, with particular emphasis on low power consumption and high code
density. In addition, the instruction set architecture has been tuned to allow a variety of micro-
architectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance
processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.
Through a quantitative approach, a large set of industry recognized benchmarks has been com-
piled and analyzed to achieve the best code density in its class. In addition to lowering the
memory requirements, a compact code size also contributes to the core’s low power characteris-
tics. The processor supports byte and halfword data types without penalty in code size and
performance.
Memory load and store operations are provided for byte, halfword, word, and double word data
with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely
linked to the architecture and is able to exploit code optimization features, both for size and
speed.
In order to reduce code size to a minimum, some instructions have multiple addressing modes.
As an example, instructions with immediates often have a compact format with a smaller imme-
diate, and an extended format with a larger immediate. In this way, the compiler is able to use
the format giving the smallest code size.
Another feature of the instruction set is that frequently used instructions, like add, have a com-
pact format with two operands as well as an extended format with three operands. The larger
format increases performance, allowing an addition and a data move in the same instruction in a
single cycle. Load and store instructions have several different formats in order to reduce code
size and speed up execution.
32-bit load/store AVR32A RISC architecture
3-stage pipeline allows one instruction per clock cycle for most instructions
MPU allows for operating systems with memory protection
– 15 general-purpose 32-bit registers
– 32-bit Stack Pointer, Program Counter and Link Register reside in register file
– Fully orthogonal instruction set
– Privileged and unprivileged modes enabling efficient and secure Operating Systems
– Innovative instruction set together with variable instruction length ensuring industry leading
– DSP extention with saturating arithmetic, and a wide variety of multiply instructions
– Byte, halfword, word and double word memory access
– Multiple interrupt priority levels
code density
AT32UC3B
17
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