AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 469
AT32UC3A364-ALUT
Manufacturer Part Number
AT32UC3A364-ALUT
Description
IC MCU 64KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A364-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
110
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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23. Two-Wire Master Interface (TWIM)
23.1
23.2
32072C–AVR32–2010/03
Features
Overview
Rev 1.0.0.1
•
•
•
•
•
•
•
The Atmel Two-wire Interface Master (TWIM) interconnects components on a unique two-wire
bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus serial
EEPROM and I²C compatible device such as a real rime clock (RTC), dot matrix/graphic LCD
controller and temperature sensor, to name a few. TWIM is always a bus master and can trans-
fer sequential or single bytes. Multiple master capability is supported. Arbitration of the bus is
performed internally and relinquishes the bus automatically if the bus arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of
core clock frequencies.
Interface in Master Mode and a full I²C compatible device.
Table 23-1.
Note:
I²C
Standard Mode Speed (100 KHz)
Fast Mode Speed (400 KHz)
7- or 10-bits Slave Addressing
START BYTE
Repeated Start (Sr) Condition
ACK and NACK Management
Slope Control and Input Filtering (Fast mode)
Clock Stretching
Compatible with I
Compatible with SMBus standard
Compatible with PMBus
Compatible with Atmel Two-Wire Interface Serial Memories
DMA interface for reducing CPU load
Arbitrary transfer lengths, including 0 data bytes
Optional clock stretching if transmit or receive buffers not ready for data transfer
– Multi-master support
– 100 and 400 kbit/s transfer speeds
– 7- and 10-bit and General Call addressing
– Hardware Packet Error Checking (CRC) generation and verification with ACK control
– SMBus ALERT interface
– 25 ms clock low timeout delay
– 10 ms master cumulative clock low extend time
– 25 ms slave cumulative clock low extend time
Standard
1. START + b000000001 + Ack + Sr
(1)
Atmel TWIM Compatibility with I²C Standard
²
C standard
Table 23-1 on page 469
lists the compatibility level of the Atmel Two-wire
Atmel TWIM
Supported
Supported
Supported
Not Supported
Supported
Supported
Supported
Supported
AT32UC3A3/A4
469
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