AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 536

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.9.13
Name:
Access Type:
Offset:
Reset value:
• RXEN: Receive Enable
• TXEN: Transmit Enable
• RXSYN: Receive Sync
• TXSYN: Transmit Sync
• CP1: Compare 1
• CP0: Compare 0
• OVRUN: Receive Overrun
• RXRDY: Receive Ready
• TXEMPTY: Transmit Empty
32072C–AVR32–2010/03
31
23
15
7
-
-
-
-
This bit is set when the CR.RXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.RXDIS bit has been written to one.
This bit is set when the CR.TXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.TXDIS bit has been written to one.
This bit is set when a Receive Sync has occurred.
This bit is cleared when the SR register is read.
This bit is set when a Transmit Sync has occurred.
This bit is cleared when the SR register is read.
This bit is set when compare 1 has occurred.
This bit is cleared when the SR register is read.
This bit is set when compare 0 has occurred.
This bit is cleared when the SR register is read.
This bit is set when data has been loaded in the RHR register while previous data has not yet been read.
This bit is cleared when the SR register is read.
This bit is set when data has been received and loaded in the RHR register.
This bit is cleared when the RHR register is empty.
This bit is set when the last data written in the THR register has been loaded in the TSR register and last data loaded in the TSR
register has been transmitted.
This bit is cleared when data remains in the THR register or is currently transmitted from the TSR register.
Status Register
30
22
14
6
-
-
-
-
SR
Read-only
0x40
0x000000CC
OVRUN
29
21
13
5
-
-
-
RXRDY
28
20
12
4
-
-
-
RXSYN
27
19
11
3
-
-
-
TXSYN
26
18
10
2
-
-
-
TXEMPTY
AT32UC3A3/A4
RXEN
CP1
25
17
9
1
-
TXRDY
TXEN
CP0
24
16
8
0
-
536