DSPIC30F2023-30I/ML Microchip Technology, DSPIC30F2023-30I/ML Datasheet - Page 11

• Manufacturer Part Number: DSPIC30F2023-30I/ML
• Description: IC DSPIC MCU/DSP 12K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2023-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core Frequency: 30MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 35
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Package: 44QFN EP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 35
• Interface Type: I2C/SPI/UART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.7.2
System operation Configuration bits are inherently
different than all other memory cells. Unlike code
memory and code-protect Configuration bits, the
system operation bits cannot be erased. If the chip is
erased with the ERASEB command, the system
operation
Consequently, you should make no assumption about
the value of the system operation bits. They should
always be programmed to their desired setting.
Configuration bits are programmed single word at
a time using the PROGC command. The PROGC
command specifies the configuration data and
Configuration register address. When Configuration
bits are programmed, any unimplemented bits must be
programmed with a ‘0’, and any reserved bits must be
programmed with a ‘1’.
Four PROGC commands are required to program all the
Configuration bits. A flowchart for Configuration bit
programming is illustrated in
5.7.3
Once the Configuration bits are programmed, the
contents of memory should be verified to ensure that
the programming is successful. Verification requires
the Configuration bits to be read back and compared
against the copy held in the programmer’s buffer. The
READD command reads back the programmed
Configuration bits and verifies that the programming
was successful.
Any unimplemented Configuration bits are read-only
and read as ‘0’.
5.7.4
The FBS and FGS Configuration registers are special
Configuration registers that control the size and level of
code protection for the Boot Segment and General
Segment, respectively. For each segment, two main
forms of code protection are provided. One form
prevents code memory from being written (write
protection), while the other prevents code memory from
being read (read protection). The dsPIC30F SMPS
family devices do not contain a Secure Segment.
© 2010 Microchip Technology Inc.
Note:
PROGRAMMING METHODOLOGY
If the General Code Segment Code
Protect bits (GSS<1:0>) are programmed
to ‘10’, code memory is code-protected
and cannot be read. Code memory must
be verified
protection. See
Guard™ Security Configuration Bits”
for more information about code-protect
Configuration bits.
PROGRAMMING VERIFICATION
CodeGuard™ SECURITY
CONFIGURATION BITS
bits
retain
before
their
Figure
Section 5.7.4 “Code-
5-5.
previous
enabling
value.
read
BWRP and GWRP bits control write protection and
BSS<2:0> and GSS<1:0> bits control read protection.
The Chip Erase ERASEB command sets all the code
protection bits to ‘1’, which allows the device to be
programmed.
When write protection is enabled, any programming
operation to code memory will fail. When read
protection is enabled, any read from code memory will
cause a ‘0x0’ to be read, regardless of the actual
contents of code memory. Since the programming
executive always verifies what it programs, attempting
to program code memory with read protection enabled
will also result in failure.
It is imperative that all code protection bits are ‘1’ while
the device is being programmed and verified. Only after
the device is programmed and verified should any of
the above bits be programmed to ‘0’.
Before performing any segment erase operation, the
programmer
dsPIC30F device has defined a Boot Segment, and
ensure that a segment does not get overwritten by
operations on any other segment.
The BSS bit field in the FBS Configuration register can
be read to determine whether a Boot Segment has
been defined. If a Boot Segment has already been
defined (and has probably already been programmed),
the user must be warned about this fact.
A Bulk Erase operation is the recommended
mechanism to allow a user to overwrite the Boot
Segment (if one chooses to do so).
In general, the segments and CodeGuard Security
related Configuration registers should be programmed
in the following order:
• FBS and Boot Segment
• FGS and General Segment
Note:
Note:
All bits in the FBS and FGS Configuration
registers can only be programmed to a
value of ‘0’. The ERASEB command (and
also the General Segment Erase in the
case of FGS) is the only way to reprogram
code-protect bits from ON (‘0’) to OFF (‘1’).
If any of the code-protect bits in FBS or
FGS is clear, then the entire device must
be erased before it can be reprogrammed.
must
first
determine
DS70284C-page 11
whether
the