AT32UC3A364S-CTUR Atmel, AT32UC3A364S-CTUR Datasheet - Page 4

• Manufacturer Part Number: AT32UC3A364S-CTUR
• Description: IC MCU 64KB FLASH 144TFBGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364S-CTUR

• Package / Case: 144-TBGA
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 66MHz
• Number Of I /o: 110
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Core Size: 32-Bit
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, I2S, JTAG, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2. Blockdiagram
Figure 2-1.
32072AS–AVR32–03/09
RESET_N
DH+,DL+
DH-,DL-
VBUS
VBG
PA
PB
PC
PX
Blockdiagram
TDO
TMS
TCK
TDI
XOUT32
XOUT0
XOUT1
XIN32
XIN0
XIN1
VBOF
32KB RAM
32KB RAM
ID
DATA[15..0]
EXTINT[7..0]
GCLK[3..0]
CMD[1..0]
AES
KPS[7..0]
CLK[2..0]
CLK
NMI_N
A[2..0]
B[2..0]
115 kHz
RCOSC
32 KHz
OSC0
OSC1
PLL0
PLL1
MSEO[1..0]
OSC
MDO[5..0]
EVTO_N
EVTI_N
INTERFACE
INTERFACE
MCKO
DMACA
USB HS
JTAG
DMA
MULTIMEDIA CARD
& MEMORY STICK
TIMER/COUNTER
CONTROLLER
CONTROLLER
CONTROLLER
GENERATOR
INTERFACE
CONTROLLER
CONTROLLER
PB
WATCHDOG
INTERRUPT
INTERRUPT
EXTERNAL
REAL TIME
MANAGER
COUNTER
BRIDGE B
CLOCK
CLOCK
S
S
S
S
POWER
SLEEP
RESET
M
M
M
HSB-PB
TIMER
CLASS 2+
0/1
NEXUS
HS
S
OCD
B
M
CONFIGURATION
INTERFACE
HIGH SPEED
MEMORY PROTECTION UNIT
BUS MATRIX
INSTR
BRIDGE A
HSB-PB
M
HSB
PB
S
UC CPU
REGISTERS BUS
INTERFACE
DATA
M
SYNCHRONOUS
CONTROLLER
INTERFACE 0/1
INTERFACE 0/1
PERIPHERAL
CONTROLLER
PERIPHERAL
CONVERTER
ANALOG TO
BITSTREAM
TWO-WIRE
USART1
USART0
USART2
USART3
DIGITAL
SERIAL
SERIAL
AUDIO
DMA
DAC
M
S
S
S
LOCAL BUS
INTERFACE
SRAM
64 KB
RX_CLOCK, RX_FRAME_SYNC
TX_CLOCK, TX_FRAME_SYNC
DSR, DTR, DCD, RI
DATAN[1..0]
MISO, MOSI
128/64 KB
NPCS[3..1]
DATA[1..0]
512/256/
RTS, CTS
RTS, CTS
TX_DATA
RX_DATA
AD[7..0]
FLASH
NPCS0
RXD
RXD
RXD
SCK
SCL
SDA
TXD
CLK
TXD
CLK
TXD
CLK
FAST GPIO
ADDR[23..0]
DATA[15..0]
NCS[5..0]
NANDOE
NANDWE
SDCKE
SDA10
SDCS1
CFCE1
CFCE2
NWAIT
SDWE
CFRW
NWE0
NWE1
NWE3
SDCK
NRD
RAS
CAS
ADVREF
PA
PB
PC
PX
AT32UC3A3
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