AT89C51RE2-RLTUM Atmel, AT89C51RE2-RLTUM Datasheet - Page 125

• Manufacturer Part Number: AT89C51RE2-RLTUM
• Description: MCU 8051 128K FLASH 44-VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-RLTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• Minimum Operating Temperature: - 40 C
• Height: 1.45 mm
• Length: 10.1 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 10.1 mm
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

WDT During Power
Down and Idle
7663E–8051–10/08
Table 93. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset value = XXXX X000
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power
Down mode the user does not need to service the WDT. There are 2 methods of exiting Power
Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior
to entering Power Down mode. When Power Down is exited with hardware reset, servicing the
WDT should occur as it normally should whenever the AT89C51RE2 is reset. Exiting Power
Down with an interrupt is significantly different. The interrupt is held low long enough for the
oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the
WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the
interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is bet-
ter to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C51RE2 while in Idle mode, the user should always set up a timer that will periodically exit
Idle, service the WDT, and re-enter Idle mode.
Number
Bit
7
-
7
6
5
4
3
2
1
0
Mnemonic
Bit
S2
S1
S0
6
-
-
-
-
-
-
Description
Reserved
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
S2
0
0
0
0
1
1
1
1
5
-
The value read from this bit is undetermined. Do not try to set this bit.
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
4
-
Selected Time-out
(2
(2
(2
(2
(2
(2
(2
(2
14
15
16
17
18
19
20
21
- 1) machine cycles, 16. 3 ms @ F
- 1) machine cycles, 32.7 ms @ F
- 1) machine cycles, 65. 5 ms @ F
- 1) machine cycles, 131 ms @ F
- 1) machine cycles, 262 ms @ F
- 1) machine cycles, 542 ms @ F
- 1) machine cycles, 1.05 s @ F
- 1) machine cycles, 2.09 s @ F
3
-
S2
2
AT89C51RE2
OSCA
OSCA
S1
OSCA
OSCA
OSCA
1
OSCA
OSCA
OSCA
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
S0
0
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