ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 488

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 28-4. Output Line Timings
28.5.8
28.5.9
488
488
Write PIO_ODSR at 1
Write PIO_ODSR at 0
Write PIO_CODR
Write PIO_SODR
SAM3S Preliminary
SAM3S Preliminary
Inputs
Input Glitch and Debouncing Filters
PIO_ODSR
PIO_PDSR
MCK
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg-
ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an
input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 Master Clock (MCK) and the
debouncing filter can filter a pulse of less than 1/2 Period of a Programmable Divided Slow
Clock.
The selection between glitch filtering or debounce filtering is done by writing in the registers
PIO_IFSCDR (PIO Input Filter Slow Clock Disable Register) and PIO_IFSCER (PIO Input Filter
Slow Clock Enable Register). Writing PIO_IFSCDR and PIO_IFSCER respectively, sets and
clears bits in PIO_IFSCSR.
The current selection status can be checked by reading the register PIO_IFSCSR (Input Filter
Slow Clock Status Register).
For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV
field of the PIO_SCDR (Slow Clock Divider Register)
Tdiv_slclk = ((DIV+1)*2).Tslow_clock
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2
Selected Clock Cycle (Selected Clock represents MCK or Divided Slow Clock depending on
PIO_IFSCDR and PIO_IFSCER programming) is automatically rejected, while a pulse with a
duration of 1 Selected Clock (MCK or Divided Slow Clock) cycle or more is accepted. For pulse
durations between 1/2 Selected Clock cycle and 1 Selected Clock cycle the pulse may or may
• If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period
• If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2
of Master Clock.
Period of the Programmable Divided Slow Clock.
APB Access
2 cycles
APB Access
2 cycles
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11