ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 825

IC MCU 32BIT 64KB FLASH 64LQFP

ATSAM3S1BA-AU

Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Datasheets

Specifications of ATSAM3S1BA-AU

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S1BA-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATSAM3S1BA-AUR
Manufacturer:
Atmel
Quantity:
10 000
35.14.8
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• CSTOCYC: Completion Signal Timeout Cycle Number
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block trans-
fers. Its value is calculated by (CSTOCYC x Multiplier).
• CSTOMUL: Completion Signal Timeout Multiplier
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block trans-
fers. Its value is calculated by (CSTOCYC x Multiplier).
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data
transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If
a non-DATA ATA command is issued, the HSMCI starts waiting immediately after the end of the response until the comple-
tion signal.
Multiplier is defined by CSTOMUL as shown in the following table:
If the data time-out set by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error flag
(CSTOE) in the HSMCI Status Register (HSMCI_SR) raises.
6500C–ATARM–8-Feb-11
31
23
15
7
Value
HSMCI Completion Signal Timeout Register
0
1
2
3
4
5
6
7
30
22
14
HSMCI_CSTOR
0x4000001C
Read-write
6
1048576
65536
Name
1024
4096
CSTOMUL
128
256
16
1
29
21
13
5
Description
CSTOCYC x 1
CSTOCYC x 16
CSTOCYC x 128
CSTOCYC x 256
CSTOCYC x 1024
CSTOCYC x 4096
CSTOCYC x 65536
CSTOCYC x 1048576
28
20
12
4
“HSMCI Write Protect Mode Register” on page
27
19
11
3
26
18
10
2
SAM3S Preliminary
CSTOCYC
25
17
9
1
840.
24
16
8
0
825

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