PIC24FJ128DA206-I/PT Microchip Technology, PIC24FJ128DA206-I/PT Datasheet - Page 253
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PIC24FJ128DA206-I/PT
Manufacturer Part Number
PIC24FJ128DA206-I/PT
Description
MCU PIC 16BIT FLASH 128K 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Specifications of PIC24FJ128DA206-I/PT
Core Size
16-Bit
Program Memory Size
128KB (43K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC24
No. Of I/o's
52
Ram Memory Size
96KB
Cpu Speed
32MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
96 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
29
Number Of Timers
5
Operating Supply Voltage
2.2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240312, DV164039
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ128DA206-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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18.6.2
In USB OTG applications, a Dual Role Device (DRD) is
a device that is capable of being either a host or a
peripheral. Any OTG DRD must support Host
Negotiation Protocol (HNP).
HNP allows an OTG B-device to temporarily become
the USB host. The A-device must first enable the
B-device to follow HNP. Refer to the “On-The-Go
Supplement to the USB 2.0 Specification” for more
information regarding HNP. HNP may only be initiated
at full speed.
After being enabled for HNP by the A-device, the
B-device requests being the host any time that the USB
link is in suspend state, by simply indicating a discon-
nect. This can be done in software by clearing
DPPULUP and DMPULUP. When the A-device detects
the disconnect condition (via the URSTIF (U1IR<0>)
interrupt), the A-device may allow the B-device to take
over as host. The A-device does this by signaling con-
nect as a full-speed function. Software may accomplish
this by setting DPPULUP.
If the A-device responds instead with resume signaling,
the A-device remains as host. When the B-device
detects
(U1IR<6>), the B-device becomes host. The B-device
drives Reset signaling prior to using the bus.
TABLE 18-3:
2010 Microchip Technology Inc.
If UVCMPSEL = 0
If UVCMPSEL = 1
V
V
CMPST
BUSVLD
0
1
0
1
0
0
0
1
the
HOST NEGOTIATION PROTOCOL
(HNP)
1
connect
EXTERNAL V
SESSVLD
V
CMPST
condition
0
0
1
1
0
0
1
1
2
BUS
(via
COMPARATOR STATES
SESSEND
ATTACHIF
1
0
0
0
PIC24FJ256DA210 FAMILY
VB_SESS_END < V
VA_SESS_VLD < V
When the B-device has finished in its role as host, it
stops all bus activity and turns on its D+ pull-up resistor
by setting DPPULUP. When the A-device detects a
suspend condition (Idle for 3 ms), the A-device turns off
its D+ pull-up. The A-device may also power-down the
V
detects the connect condition (via ATTACHIF), the
A-device resumes host operation and drives Reset
signaling.
18.6.3
The external V
ting the UVCMPDIS bit (U1CNFG2<1>). This disables
the internal V
attach V
The external comparator interface uses either the
V
SESSVLD and SESSEND pins, based upon the setting
of the UVCMPSEL bit (U1CNFG2<5>). These pins are
digital inputs and should be set in the following patterns
(see Table 18-3), based on the current level of the V
voltage.
BUS
CMPST
V
VB_SESS_END < V
VA_SESS_VLD < V
BUS
V
BUS
supply to end the session. When the A-device
Bus Condition
< VB_SESS_END
1 and V
BUS
> VBUS_VLD
V
EXTERNAL V
BUS
BUS
to the microcontroller’s V
BUS
V
BUS
BUS
BUS
Bus Condition
< VA_VBUS_VLD
< VB_SESS_END
< VA_SESS_VLD
comparators, removing the need to
comparator option is enabled by set-
CMPST
> VBUS_VLD
BUS
BUS
2 pins, or the V
< VA_VBUS_VLD
< VA_SESS_VLD
BUS
COMPARATORS
DS39969B-page 253
BUS
pin.
BUSVLD
BUS
,
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