AT90CAN64-16AU Atmel, AT90CAN64-16AU Datasheet - Page 192

• Manufacturer Part Number: AT90CAN64-16AU
• Description: IC MCU AVR 64K FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Device Core: AVR
• Family Name: 90C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 53
• Interface Type: JTAG/SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Processor Series: AT90CANx
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR CAN
• No. Of I/o's: 53
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Cpu Family: 90C
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.9.3
192
AT90CAN32/64/128
Asynchronous Operational Range
Figure 17-7
of the next frame.
Figure 17-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table
bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
D
S
S
S
R
R
Table 17-2
that Normal Speed mode has higher toleration of baud rate variations.
F
M
slow
fast
R
(U2Xn = 0)
(U2Xn = 1)
slow
Sum of character size and parity size (D = 5 to 10 bit)
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode.
First sample number used for majority voting. S
S
is the ratio of the fastest incoming data rate that can be accepted in relation to the
receiver baud rate.
17-2) base frequency, the Receiver will not be able to synchronize the frames to the start
Sample
Sample
F
Middle sample number used for majority voting. S
S
is the ratio of the slowest incoming data rate that can be accepted in relation to
the receiver baud rate.
RxDn
= 4 for Double Speed mode.
M
=
and
= 5 for Double Speed mode.
shows the sampling of the stop bit and the earliest possible beginning of the start bit
------------------------------------------ -
S 1
–
Table 17-3
(
D
+
Figure
+
D S ⋅
1
)S
1
1
+
17-7. For Double Speed mode the first low level must be delayed to
list the maximum receiver baud rate error that can be tolerated. Note
S
2
F
3
2
4
5
3
6
7
4
STOP 1
R
8
fast
F
9
5
=
= 8 for normal speed and
10
-----------------------------------
(
M
D
= 9 for normal speed and
(
0/1
(A)
+
D
6
1
+
)S
0/1
2
)S
+
(B)
0/1
0/1
S
M
7679H–CAN–08/08
(C)