AT90CAN64-16AU Atmel, AT90CAN64-16AU Datasheet - Page 48

• Manufacturer Part Number: AT90CAN64-16AU
• Description: IC MCU AVR 64K FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Device Core: AVR
• Family Name: 90C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 53
• Interface Type: JTAG/SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Processor Series: AT90CANx
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR CAN
• No. Of I/o's: 53
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Cpu Family: 90C
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.5
Table 6-2.
Notes:
6.6
6.6.1
48
Sleep
Mode
Idle
ADC Noise
Reduction
Power-
down
Power-
save
Standby
Standby Mode
1. Only recommended with external crystal or resonator selected as clock source.
2. If AS2 bit in ASSR is set.
3. Only INT3:0 or level interrupt INT7:4.
Minimizing Power Consumption
(1)
AT90CAN32/64/128
Analog to Digital Converter
clk
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
CPU
Active Clock Domains
clk
FLASH
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2
will run during sleep. The device can wake up from either Timer Overflow or Output Compare
event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in
TIMSK2, and the global interrupt enable bit in SREG is set.
If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recommended
instead of Power-save mode because the contents of the registers in the asynchronous timer
should be considered undefined after wake-up in Power-save mode if AS2 is 0.
This sleep mode basically halts all clocks except clk
modules, including Timer/Counter2 if clocked asynchronously.
When the SM2..0 bits are 110 and an External Crystal/Resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in 6 clock cycles.
There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possible of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to
273
for details on ADC operation.
clk
X
IO
clk
X
X
ADC
clk
X
X
X
(2)
ASY
Enabled
Source
Clock
Main
X
X
X
Oscillators
Enabled
Timer
Osc.
X
X
X
(2)
(2)
(2)
INT7:0
X
X
X
X
X
(3)
(3)
(3)
(3)
ASY
“Analog to Digital Converter - ADC” on page
, allowing operation only of asynchronous
Address
Match
TWI
X
X
X
X
X
Wake-up Sources
Timer
X
X
X
2
(2)
(2)
EEPROM
Ready
SPM/
X
X
7679H–CAN–08/08
ADC
X
X
Other
I/O
X