ATXMEGA192D3-AU Atmel, ATXMEGA192D3-AU Datasheet - Page 42

MCU AVR 192K FLASH 64TQFP

ATXMEGA192D3-AU

Manufacturer Part Number
ATXMEGA192D3-AU
Description
MCU AVR 192K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheets

Specifications of ATXMEGA192D3-AU

Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
192KB (96K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
ATXMEGA
No. Of I/o's
50
Eeprom Memory Size
2KB
Ram Memory Size
16KB
Cpu Speed
32MHz
Rohs Compliant
Yes
Processor Series
XMEGA
Core
AVR
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
50
Number Of Timers
5
Operating Supply Voltage
2.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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8068T–AVR–12/10
Figure 25-1. ADC overview
Each ADC has four MUX selection registers with a corresponding result register. This means
that four channels can be sampled within 1.5 µs without any intervention by the application other
than starting the conversion. The results will be available in the result registers.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop-
agation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB,
respectively.
Channel C MUX selection
Channel D MUX selection
Channel A MUX selection
Channel B MUX selection
1-64 X
Reference selection
Configuration
ADC
Trigger
Event
Channel A
Channel B
Channel C
Channel D
Register
Register
Register
Register
XMEGA A3
42

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