DSPIC30F5015-30I/PT Microchip Technology, DSPIC30F5015-30I/PT Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 66KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F501530IPT

dsPIC30F5015/5016
TABLE 2:
DS80452C-page 2
Operations
Note 1:
Compare
Compare
Module
Output
Output
Sleep
Mode
Timer
I
PWM
CPU
ADC
ADC
PSV
2
QEI
QEI
PLL
I
I
I
I/O
C™
2
2
2
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Debug Mode
Sleep Mode
Slave Mode
Sleep Mode
PWM Mode
Error Count
Lock Status
Multiplexed
Addressing
Addressing
Addressing
Generation
Instruction
Detection
Sampling
Interrupt
SILICON ISSUE SUMMARY
Feature
Port Pin
with IC1
10-bit
10-bit
10-bit
DISI
Rate
bit
—
—
—
Number
Item
10.
12.
13.
14.
15.
16.
17.
11.
9.
1.
2.
3.
4.
5.
6.
7.
8.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
The output compare module will produce a glitch on the output
when an I/O pin is initially set high and the module is configured
to drive the pin low at a specified time.
Output compare will produce a glitch when loading 0% duty
cycle in PWM mode. It will also miss the next compare after the
glitch.
The Index Pulse Reset mode of the QEI does not work properly
when used along with error count detection. When counting
upwards, the POSCNT register will increment one extra count
after the index pulse is received. The extra count will
generate a false count error interrupt.
ADC event triggers from the INT0 pin will not wake-up the
device from Sleep mode if the SMPI bits are non-zero.
The 10-bit Analog-to-Digital Converter (ADC) has a maximum
sampling rate of 750 ksps.
The QEI module does not generate an interrupt in a particular
overflow condition.
Execution of the Sleep instruction (PWRSAV #0) may cause
incorrect program operation after the device wakes up from
Sleep. The current consumption during Sleep may also
increase beyond the specifications listed in the device data
sheet.
The I
an I
PTMR does not continue counting down after halting code
execution in Debug mode.
The Port I/O pin multiplexed with the Input Capture 1 (IC1)
function cannot be used as a digital input pin when the UART
auto-baud feature is enabled.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
Clock switching prevents the device from waking up from
Sleep.
The PLL LOCK Status bit (OSCCON<5>) can occasionally get
cleared and generate an oscillator failure trap even when the
PLL is still locked and functioning correctly.
An address error trap occurs in certain addressing modes when
accessing the first four bytes of any PSV page.
The 10-bit slave does not set the RBF flag or load the I2CxRCV
register on address match if the Least Significant bits (LSbs) of
the address are the same as the 7-bit reserved addresses.
When the I
address of 0x102, the I2CxRCV register content for the lower
address byte is 0x01 rather than 0x02.
2
C slave.
2
C module loses incoming data bytes when operating as
2
2
C module is configured for 10-bit addressing using
C module is configured as a 10-bit slave with an
Issue Summary
2
C devices, the
© 2010 Microchip Technology Inc.
Revisions
Affected
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)