ATSAM3S2AA-AU Atmel, ATSAM3S2AA-AU Datasheet - Page 561
ATSAM3S2AA-AU
Manufacturer Part Number
ATSAM3S2AA-AU
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S2AA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
34
Ram Memory Size
32KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S2AA-AU
Manufacturer:
AMD
Quantity:
101
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29.9.5
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• CKS: Transmit Clock Selection
• CKO: Transmit Clock Output Mode Selection
• CKI: Transmit Clock Inversion
0 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal
input is sampled on Transmit clock rising edge.
1 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal
input is sampled on Transmit clock falling edge.
CKI affects only the Transmit Clock and not the output clock signal.
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Value
Value
3-7
31
23
15
0
1
2
3
0
1
2
–
7
SSC Transmit Clock Mode Register
CKG
Name
MCK
TK
RK
Name
NONE
CONTINUOUS
TRANSFER
30
22
14
SSC_TCMR
0x40004018
Read-write
–
6
Description
Divided Clock
TK Clock signal
RK pin
Reserved
Description
None
Continuous Receive Clock
Transmit Clock only during data transfers
Reserved
CKI
29
21
13
–
5
28
20
12
–
4
PERIOD
STTDLY
“SSC Write Protect Mode Register”
CKO
27
19
11
3
TK Pin
Input-only
Output
Output
26
18
10
2
SAM3S Preliminary
SAM3S Preliminary
START
.
25
17
9
1
CKS
24
16
8
0
561
561
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