ATSAM3S2AA-AU Atmel, ATSAM3S2AA-AU Datasheet - Page 839
ATSAM3S2AA-AU
Manufacturer Part Number
ATSAM3S2AA-AU
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S2AA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
34
Ram Memory Size
32KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S2AA-AU
Manufacturer:
AMD
Quantity:
101
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35.14.16 HSMCI Configuration Register
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• FIFOMODE: HSMCI Internal FIFO control mode
0 = A write transfer starts when a sufficient amount of data is written into the FIFO.
When the block length is greater than or equal to 3/4 of the HSMCI internal FIFO size, then the write transfer starts as soon
as half the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer
starts as soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is
written in the internal FIFO.
1 = A write transfer starts as soon as one data is written into the FIFO.
• FERRCTRL: Flow Error flag reset control mode
0= When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag.
1= When an underflow/overflow condition flag is set, a read status resets the flag.
• HSMODE: High Speed Mode
0= Default bus timing mode.
1= If set to one, the host controller outputs command line and data lines on the rising edge of the card clock. The Host
driver shall check the high speed support in the card registers.
• LSYNC: Synchronize on the last block
0= The pending command is sent at the end of the current data block.
1= The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall
be different from zero)
6500C–ATARM–8-Feb-11
31
23
15
–
–
7
–
30
22
14
HSMCI_CFG
0x40000054
Read-write
–
–
6
–
29
21
13
–
–
–
5
–
FERRCTRL
LSYNC
28
20
12
–
–
4
“HSMCI Write Protect Mode Register” on page
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
–
SAM3S Preliminary
25
17
–
–
9
–
1
–
840.
FIFOMODE
HSMODE
24
16
–
–
8
0
839
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